Memory System And Data Transmission Method Patent Application (2024)

U.S. patent application number 17/321209 was filed with the patent office on 2021-09-02 for memory system and data transmission method.The applicant listed for this patent is LONGITUDE LICENSING LIMITED. Invention is credited to Yoshinori Matsui.

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

Abstract

A memory system of a high-speed operation can be realized byreducing an influence of reflection signals etc. caused bybranching and impedance mismatching in various wirings between amemory controller and a memory module, and an influence due totransmission delays of data, command/address, and clocks in thememory module. To this end, a memory system comprises a memorycontroller and a memory module mounted with DRAMs. A buffer ismounted on the memory module. The buffer and the memory controllerare connected to each other via data wiring, command/addresswiring, and clock wiring. The DRAMs and the buffer on the memorymodule are connected to each other via internal data wiring,internal command/address wiring, and internal co*ck wiring. The datawiring, the command/address wiring, and the clock wiring may beconnected to buffers of other memory modules in cascade. Betweenthe DRAMs and the buffer on the memory module, high-speed datatransmission is implemented using data phase signals synchronouswith clocks.

Related U.S. Patent Documents

Foreign Application Data

Claims

1. A method for operating a memory controller comprising:outputting a clock signal on a clock terminal; outputting acommand/address signal in synchronization with the clock signal oncommand/address terminals; outputting a write data signal on a dataterminal; outputting a write data timing signal in synchronizationwith the write data signal on a data timing terminal; and insertinga delay between the clock signal and the write data timing signalto compensate for a difference in delay between the clock signaland the write data timing signal from the memory controller to amemory device.

2. The method as claimed in claim 1, further comprising: receivinga read data signal on the data terminals; and receiving a read datatiming signal in synchronization with the read data signal on thedata timing terminal.

3. The method as claimed in claim 1, wherein an edge of the clocksignal is aligned between edges of the command/address signal.

4. The method as claimed in claim 1, wherein an edge of the writedata timing signal is aligned between edges of the write datasignal.

5. The method as claimed in claim 1, wherein an edge of the writedata timing signal is aligned with an edge of the write datasignal.

6. The method as claimed in claim 1, wherein the write data signalis a double data rate (DDR) signal.

7. The method as claimed in claim 1, wherein the write data timingsignal is a data strobe (DQS) signal.

8. The method as claimed in claim 1, wherein the write data timingsignal has the same frequency as the clock signal.

9. The method as claimed in claim 1, wherein the write data timingsignal is a write data phase (DPS) signal.

10. The method as claimed in claim 1, wherein the write data timingsignal has a frequency lower than the frequency of the clocksignal.

11. The method as claimed in claim 10, wherein the write datatiming signal has a frequency equal to 25% of the frequency of theclock signal.

12. The method as claimed in claim 1, wherein the delay is apositive delay.

13. The method as claimed in claim 1, wherein the delay is anadjustable delay.

14. The method as claimed in claim 1, wherein the delay is a fixeddelay.

15. The method as claimed in claim 14, wherein the delay isapproximately equal to one half a period of the clock.

16. A method for operating a memory system, the method comprising:outputting a clock signal on a clock terminal of a memorycontroller; outputting a command/address signal synchronized to theclock signal on command/address terminals of the memory controller;outputting a write data signal on data terminals of the memorycontroller; and outputting a write data timing signal synchronizedto the write data signal on a data timing terminal of the memorycontroller; receiving the clock signal on a clock terminal of amemory device; receiving the command/address signal oncommand/address terminals of the memory device; receiving the writedata signal on data terminals of the memory device; and receivingthe write data timing signal a data timing terminal of the memorydevice; inserting a delay between the write data timing signal andthe clock signal at the memory controller to compensate for adifference in delay between the clock signal and the write datatiming signal received by the memory device.

17. The method as claimed in claim 16, wherein an edge of the clocksignal is aligned between edges of the command/address signal.

18. The method as claimed in claim 16, wherein an edge of the writedata timing signal is aligned between edges of the write datasignal.

19. The method as claimed in claim 16, wherein an edge of the writedata timing signal is aligned with an edge of the write datasignal.

20. The method as claimed in claim 16, wherein the data signal is adouble data rate (DDR) signal.

21. The method as claimed in claim 16, wherein the write datatiming signal is a data strobe (DQS) signal.

22. The method as claimed in claim 16, wherein the write datatiming signal has the same frequency as the clock signal.

23. The method as claimed in claim 16, wherein the write datatiming signal is a data phase (DPS) signal.

24. The method as claimed in claim 16, wherein the write datatiming signal has a frequency lower than the frequency of the clocksignal.

25. The method as claimed in claim 24, wherein the write datatiming signal has a frequency equal to 25% of the frequency of theclock signal.

26. The method as claimed in claim 16, wherein the delay is apositive delay.

27. The method as claimed in claim 16, wherein the delay is anadjustable delay.

28. The method as claimed in claim 16, wherein the delay is a fixeddelay.

29. The method as claimed in claim 28, wherein the delay isapproximately equal to one half a period of the clock signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patentapplication Ser. No. 12/270,546, filed on Nov. 13, 2008, which is adivisional of U.S. Pat. No. 7,467,317 granted Dec. 16, 2008, whichis a divisional of U.S. Pat. No. 7,155,627 granted Dec. 26, 2006,the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

Field of the Invention

[0002] The present invention relates to a memory system having aconfiguration that enables high-speed operation, and furtherrelates to a data transmission system that is used in the memorysystem.

Description of the Related Art

[0003] Conventionally, in the memory systems of this type,interfaces have been studies that enable operations at high speedand with low signal amplitude. As a standard for such interfaces,SSTL (Stub Series Terminated Transceiver Logic) has been proposed.Further, with respect to the memory systems having DRAMs as memorydevices, there have been proposed such memory systems employing aDDR (Double Data Rate) system wherein a data transmission speed canbe twice by inputting/outputting data synchronously with both edgesof rise (leading edge) and fall (trailing edge) of clocks, therebyto operate the DRAMs at high speed.

[0004] Conventionally, as a memory system employing the foregoingSSTL and DDR, there has been proposed such a memory system whereina plurality of memory modules are mounted on a mother board, andthese memory modules are controlled by a memory controller called achipset. In this case, a plurality of DRAMs are mounted on eachmemory module.

[0005] As a memory system of this type, JP-A-2001-256772(hereinafter referred to as "Reference 1") discloses a memorysystem wherein a plurality of memory modules each mounted with aplurality of DRAMs are mounted on a mother board. The disclosedmemory module comprises a plurality of DRAMs arranged on arectangular memory module board in parallel in a longitudinaldirection thereof, and a command/address buffer and a PLL chip fordistributing clocks to the DRAMs, which are disposed between theDRAMs. Each DRAM on the memory module board is connected to moduledata wiring extending in a short-side direction of the moduleboard, while the command/address buffer and the PLL chip areconnected to module command/address wiring and module clock wiringextending in the short-side direction of the module board. Further,for distributing commands/addresses and clocks to the DRAMs fromthe command/address buffer and the PLL chip, module command/addressdistributing wiring and module clock distributing wiring are drawnout in the longitudinal direction of the module board.

[0006] In this configuration, data signals are directly given tothe DRAMs on each memory module from a memory controller providedon the mother board, while command/address signals and clocksignals are given to the DRAMs on each memory module from thememory controller via the command/address buffer and the PLL chip,respectively. In the memory system using the foregoing memorymodules, when the single memory module is taken into consideration,it is hardly necessary to form branch wiring on the memory modulerelative to signal wiring on the mother board. Therefore, there isa merit that it is possible to reduce waveform distortion ordisturbance due to undesirable signal reflection caused by branchwiring. Further, there is also a merit that access time can beshortened.

[0007] JP-A-H10-293635 (hereinafter referred to as "Reference 2")discloses a memory system wherein a memory controller and aplurality of memory modules are mounted on a mother board. Thedisclosed memory system ensures a setup time and a hold time ofeach memory module to enable high-speed signal transfer by matchingpropagation times of clock signals and data signals outputted fromthe memory controller. Further, Reference 2 also describes a methodof stably feeding clocks. Specifically, clocks that have twiceinputted clocks in frequency are produced, and signals and outputsof SDRAMs are controlled synchronously with the produced clocks ina memory module or memory LSI. In this connection, Reference 2,FIG. 28, shows a configuration wherein clocks having a frequency of2.PHI. are produced at the memory controller, and the clocks aredivided to half in frequency so as to be clocks having a frequencyof .PHI., then transmitted to the memory module.

[0008] Further, Reference 2, FIG. 34, shows a configuration whereinthe clock frequency given from the memory controller is made twiceand fed to memories in the memory module. Accordingly, Reference 2discloses a technique wherein clocks of a predetermined frequencyare transmitted/received between the memory controller and thememory module, and the frequency of the clocks is increased twicein the memories such as SDRAMs or the memory controller. In otherwords, Reference 2 describes that the frequency lower than theclock frequency within the memory is transmitted/received betweenthe memory module and the memory controller.

[0009] In Reference 1, the module data wiring extending in theshort-side direction of the module board, and the modulecommand/address distributing wiring and the module clockdistributing wiring drawn out onto the DRAMs from thecommand/address buffer and the PLL chip have different lengths fromeach other. Therefore, data arrives at each DRAM at timing thatdiffers from arrival timing of command/address and clock signals,and thus, it is difficult to adjust the timing therebetween.

[0010] On the other hand, in Reference 2, inasmuch as the clockshaving the frequency lower than the clock frequency within thememory module are transmitted/received between the memorycontroller and the memory module, a data transfer time isprolonged. Further, in the configuration of Reference 2, since thetransfer speed of data can not exceed the operation speed of thememory, there arises a limitation about the speedup and the numberof memory modules that can be mounted. In addition, Reference 1 and2 teaches nothing about a technique of transmitting data at highspeed between the memory controller and the memory module.

SUMMARY OF THE INVENTION

[0011] Therefore, it is an object of the present invention toprovide a memory system that can easily adjust timing between datasignals, and command/address and clock signals in each memorymodule.

[0012] It is another object of the present invention to provide amemory system that can reduce reflection signals caused bybranching and impedance mismatching and, as a result, that canoperate at high speed.

[0013] It is still another object of the present invention toprovide a data transfer method that can transfer data at high speedbetween two circuits provided in a module.

[0014] A specific object of the present invention is to provide adata transfer method that can transfer data at high speed between abuffer and DRAMs in a memory module.

[0015] According to the present invention, there is obtained amemory system wherein a buffer having a predetermined function ismounted on a memory module, and point-to-point connection isprovided between a memory controller and a memory module andbetween memory modules. According to this configuration, signalquality at high frequencies can be improved. Further, signalwirings between the buffer and DRAMs on the memory module can beconnected using wiring layout that includes only electricallyignorable branching and does not have electrically influentialbranching, which results in improvement of the signal quality.

[0016] Further, according to the present invention, a higher speedmemory system can be realized by using a datatransmission/reception system employing bidirectional data phasesignals on each memory module.

[0017] Here, explanation will be given about a buffer according tothe present invention. The buffer or buffers are provided on amemory module. Data wiring between a memory controller and a memorymodule or between memory modules is connected to a buffer on thememory module in a grouped fashion. In a memory system providedwith a plurality of memory modules, buffers on the adjacent memorymodules are connected to each other via data lines in apoint-to-point fashion. In this case, a data signal is transferredon the data lines at a speed that is n times relative to a datafrequency of a DRAM. Further, when compressed into packets andmultiplexed, the number of data lines is reduced to about 1/n (notnecessarily 1/n because there is actually an indivisible case orthe like).

[0018] On the other hand, command/address wiring is connected tothe memory controller and between the buffers of the memory modulesper group of data wiring and, like the data wiring, ispoint-to-point connected between the memory controller and thememory module and between the memory modules. A command/addresssignal is transferred at a speed that is m times a command/addresssignal frequency of the DRAM and, when compressed into packets, thenumber of signal lines is reduced to about 1/m (also notnecessarily 1/m because there is actually an indivisible case orthe like).

[0019] The buffer provided on each memory module has a function ofreceiving a data signal or a command/address signal from the memorycontroller or the memory module of the prior stage, encodingpackets of the data or command/address signal to provide the numberof signals corresponding to the DRAMs on the subject memory module,and transmitting them to the DRAMs at a 1/n or 1/m times frequency.Further, the buffer also has a function of transferring ortransmitting a command/address signal to the cascade-connectedmemory module of the next stage, and a function of bidirectionallytransmitting/receiving a data signal relative to the next-stagememory module. The respective signals on the memory modules areconnected with wiring layout having only such branching that can beelectrically ignored. Identification of a packet transmissiondestination of the data or command/address signal is carried outusing a module ID signal.

[0020] Characteristic aspects or modes of the present inventionwill be enumerated hereinbelow.

[0021] According to a first mode of the present invention, there isobtained a memory system having a module mounted with a pluralityof memory circuits, and a controller for controlling the pluralityof memory circuits, characterized in that the module is mountedwith at least one buffer connected to the controller via datawiring for data transmission, and the buffer and the plurality ofmemory circuits are connected to each other via internal datawiring in the module.

[0022] According to a second mode of the present invention, thereis obtained a memory system according to the first mode, whereinthe module is mounted with a plurality of buffers, and theplurality of buffers are connected to the controller via the datawiring.

[0023] According to a third mode of the present invention, there isobtained a memory system according to the first or second mode,wherein the buffer is further connected to the controller viacommand/address wiring and clock wiring.

[0024] According to a fourth mode of the present invention, thereis obtained a memory system according to the third mode, whereinthe buffer is connected to the memory circuits via internalcommand/address wiring and internal clock wiring corresponding tothe command/address wiring and the clock wiring, respectively.

[0025] According to a fifth mode of the present invention, there isobtained a memory system according to the fourth mode, wherein theinternal command/address wiring and the internal clock wiring arecommonly used for the memory circuits.

[0026] According to a sixth mode of the present invention, there isobtained a memory system according to any one of the first to fifthmodes, wherein each of the memory circuits is a DRAM, and data istransmitted/received bidirectionally in the data wiring between thecontroller and the buffer.

[0027] According to a seventh mode of the present invention, thereis obtained a memory system having a plurality of modules eachmounted with a plurality of memory circuits, and a controller forcontrolling the memory circuits of the plurality of modules,characterized in that each of the modules is provided with at leastone buffer, and the buffer of each module is connected to thebuffer of another module and/or the controller via data wiring fordata transmission.

[0028] According to an eighth mode of the present invention, thereis obtained a memory system according to the seventh mode, whereinthe buffer of each module is connected to the buffer of anothermodule and/or the controller via command/address wiring and clockwiring.

[0029] According to a ninth mode of the present invention, there isobtained a memory system according to the seventh or eighth mode,wherein the data wiring forms a daisy chain by connecting thebuffers of the plurality of modules and the controller incascade.

[0030] According to a tenth mode of the present invention, there isobtained a memory system according to the seventh mode, whereineach of the buffers of the plurality of modules is directlyconnected to the controller via the data wiring.

[0031] According to an eleventh mode of the present invention,there is obtained a memory system according to the tenth mode,wherein each of the buffers of the plurality of modules is furtherdirectly connected to the controller via command/address wiring andclock wiring.

[0032] According to a twelfth mode of the present invention, thereis obtained a memory system according to the eleventh mode, furthercomprising buffers provided on other modules and each connected toone of the buffers in cascade via data wiring, command/addresswiring, and clock wiring.

[0033] According to a thirteenth mode of the present invention,there is obtained a memory system according to any one of theeighth to twelfth modes, wherein the memory circuits of each moduleare grouped into a plurality of ranks, and the memory circuits,belonging to the same rank, of the plurality of modules aresimultaneously accessible.

[0034] According to a fourteenth mode of the present invention,there is obtained a memory system according to the twelfth orthirteenth mode, wherein a data transmission speed on the datawiring is higher than a data transmission speed on internal datawiring between the buffer and each of the memory circuits on eachmodule.

[0035] According to a fifteenth mode of the present invention,there is obtained a memory system according to the fourteenth mode,wherein transmission speeds on the command/address wiring and theclock wiring are higher than transmission speeds on internalcommand/address wiring and internal clock wiring, corresponding tothe command/address wiring and the clock wiring, between the bufferand the memory circuits on each module.

[0036] According to a sixteenth mode of the present invention,there is obtained a memory system according to the fourteenth mode,wherein data for the buffers of the plurality of modules aretransmitted in the data wiring in the form of a packet, and thebuffers separate the data in the form of the packet.

[0037] According to a seventeenth mode of the present invention,there is obtained a memory system according to the fifteenth mode,wherein commands/addresses and clocks for the buffers of theplurality of modules are transmitted in the command/address wiringand the clock wiring in the form of packets, and each of thebuffers has a function of separating the commands/addresses anddividing the clocks in frequency.

[0038] According to an eighteenth mode of the present invention,there is obtained a memory system having a module mounted with abuffer and a memory circuit connected to the buffer, and a memorycontroller connected to the buffer on the module, characterized inthat a transmission speed between the memory controller and thebuffer is higher than a transmission speed between the buffer onthe module and the memory circuit connected to the buffer.

[0039] According to a nineteenth mode of the present invention,there is obtained a memory system according to the eighteenth mode,wherein a plurality of modules each having the buffer and thememory circuit are provided, and the buffers of the respectivemodules are connected in turn in cascade relative to the memorycontroller via data wiring, command/address wiring, and clockwiring, and wherein the memory circuit and the buffer are connectedto each other on each module via internal data wiring, internalcommand/address wiring, and internal clock wiring, and transmissionspeeds on the data wiring, the command/address wiring, and theclock wiring are higher than transmission speeds on the internaldata wiring, the internal command/address wiring, and the internalclock wiring.

[0040] According to a twentieth mode of the present invention,there is obtained a memory system according to the nineteenth mode,wherein the memory circuit of each module is a DRAM, data phasesignals are transmitted bidirectionally between the buffer and theDRAM on each module at timing that avoids collision therebetween,and each of the DRAM and the buffer produces internal clocks basedon the received data phase signal and performsreception/transmission of data according to the internalclocks.

[0041] According to a twenty-first mode of the present invention,there is obtained a data transmission method fortransmitting/receiving data bidirectionally between a first and asecond device, the first device receiving data according to firstinternal clocks, and the second device receiving data according tosecond internal clocks, characterized in that a first and a seconddata phase signal are continuously transmitted bidirectionally onthe same wiring between the first and second devices at timing thatavoid collision therebetween, the first device refers to timing ofthe first data phase signal to thereby transmit data to the seconddevice, while the second device refers to timing of the second dataphase signal to thereby transit data to the first device.

[0042] According to a twenty-second mode of the present invention,there is obtained a data transmission method according to thetwenty-first mode, wherein the second device produces the secondinternal clocks according to the received first data phase signaland receives the data from the first device according to the secondinternal clocks, while the first device produces the first internalclocks according to the received second data phase signal, producesthe second data phase signal according to the first internalclocks, and receives the data from the second device according tothe first internal clocks.

[0043] According to a twenty-third mode of the present invention,there is obtained a data transmission method according to thetwenty-first or twenty-second mode, wherein the first devicesuppresses, of the first and second data phase signals transmittedbidirectionally, the first data phase signal outputted from thefirst device, while the second device suppresses, of the first andsecond data phase signals transmitted bidirectionally, the seconddata phase signal outputted from the second device.

[0044] According to a twenty-fourth mode of the present invention,there is obtained a data transmission method according to any oneof the twenty-first to twenty-third modes, wherein the first andsecond devices are a buffer and a DRAM, respectively, and the DRAMis given external clocks and produces the second internal clocksbased on the external clocks and the received first data phasesignal.

[0045] According to a twenty-fifth mode of the present invention,there is obtained a data transmission method according to any oneof the twenty-first to twenty-third modes, wherein the first andsecond devices produce the first and second internal clocks fromthe second and first data phase signals using DLLs.

[0046] According to a twenty-sixth mode of the present invention,there is obtained a data transmission system fortransmitting/receiving data between a first and a second device,characterized in that a transmission side of the first and seconddevices has means for transmitting, upon transmission of the data,a data phase signal representing a predetermined phase of the datacontinuously irrespective of transmission of the data, and areception side of the first and second devices has means forreproducing internal clocks of the reception side based on the dataphase signal and receiving the data according to the reproducedinternal clocks.

[0047] According to a twenty-seventh mode of the present invention,there is obtained a data transmission system fortransmitting/receiving data bidirectionally between a first and asecond device, characterized in that each of the first and seconddevices has transmission means for transmitting, upon transmissionof the data, a data phase signal representing a predetermined phaseof the data continuously irrespective of transmission of the data,and transmitting the data based on the data phase signal, andreception means for reproducing data reception internal clocksbased on the data phase signal and receiving the data according tothe reproduced internal clocks.

[0048] According to a twenty-eighth mode of the present invention,there is obtained a data transmission system according to thetwenty-seventh mode, wherein the first and second devices are abuffer and a DRAM, respectively, transmission means of the bufferhas means for outputting a write data phase signal to the DRAM asthe data phase signal, reception means of the buffer has means forreceiving a read data phase signal from the DRAM as the data phasesignal, reception means of the DRAM has means for reproducing thedata reception internal clocks from the write data phase signal,and means for receiving the data according to the reproducedinternal clocks, and transmission means of the DRAM has means foroutputting a read data phase signal as the data phase signal attiming relying on the received write data phase signal.

[0049] According to a twenty-ninth mode of the present invention,there is obtained a data transmission system according to thetwenty-eighth mode, wherein the write data phase signal and theread data phase signal are bidirectionally transmitted onto thesame signal line at mutually different timings

[0050] According to a thirtieth mode of the present invention,there is obtained a data transmission system according to thetwenty-eighth mode, wherein the write data phase signal and theread data phase signal are bidirectionally transmitted ontomutually different signal lines at mutually different timings.

[0051] According to a thirty-first mode of the present invention,there is obtained a data transmission system according to any oneof the twenty-eighth to thirtieth modes, wherein the read dataphase signal reception means of the buffer has means forreproducing data reception buffer internal clocks based on bufferinternal clocks and the read data phase signal, and the read dataphase signal output means of the DRAM has means for reproducingDRAM internal clocks for outputting the read data phase signal,based on external clocks and the write data phase signal.

[0052] When speeding up the foregoing memory systems, it ispreferable to employ the following configurations taking intoaccount a skew on each memory module.

[0053] Specifically, according to a mode of the present invention,there is obtained a memory module having a plurality of memorycircuits and a buffer, wherein a command/address signal istransmitted from the buffer to the plurality of memory circuits,and data signals following the command/address signal aretransmitted/received between the buffer and the plurality of memorycircuits, characterized in that at least one of the plurality ofmemory circuits and the buffer has skew absorbing means forabsorbing timing skews that are generated between thecommand/address signal and the data signals depending on mountingpositions of the memory circuits. When each of the memory circuitsis a DRAM, it is preferable that the command/address signal isoutputted synchronously with buffer clocks outputted from thebuffer to the memory circuits.

[0054] When employing such a configuration, it is preferable thatthe skew absorbing means are provided in the plurality of memorycircuits and the buffer, respectively, and that the data signalsare transmitted/received between the plurality of DRAMs and thebuffer synchronously with data phase signals representing phases ofthe data signals.

[0055] Here, it is preferable that each of the DRAMs is given acommand/address signal from the buffer synchronously with thebuffer clocks and further given a write data phase signal (WDPS)from the buffer as the data phase signal, and the skew absorbingmeans of the DRAM has means for producing a plurality of phaseclocks for receiving the command/address signal according to thebuffer clocks, means for producing data reception DRAM internalphase clocks from the WDPS, and means for domain-crossing thecommand/address signal received synchronously with the phaseclocks, to the data reception DRAM internal phase clocks.

[0056] On the other hand, the DRAM outputs a read data phase signal(RDPS) to the buffer as the data phase signal, and the skewabsorbing means of the buffer has means for producing datareception buffer internal phase clocks from the RDPS received fromthe DRAM, means for producing buffer internal phase clocks based onthe WDPS, and means for causing a read data signal inputtedsynchronously with the RDPS, to match with the buffer internalphase clocks.

[0057] According to another mode of the present invention, there isobtained a memory module, wherein the DRAM is given a write dataphase signal (WDPS) from the buffer as the data phase signal, andinputted with a data signal synchronously with the WDPS, and theskew absorbing means of the DRAM has means for producing datareception DRAM internal phase clocks from the WDPS, means forproducing a plurality of phase clocks from the buffer clocks, andmeans for domain-crossing a data signal received synchronously withthe data reception DRAM internal phase clocks, to the plurality ofphase clocks.

[0058] Here, it is preferable that the DRAM outputs a read dataphase signal (RDPS) based on buffer clocks, and the skew absorbingmeans of the buffer has means for producing data reception bufferinternal phase clocks based on the RDPS, means for producing bufferinternal phase clocks based on global clocks, and means for causinga data signal read from the DRAM and received according to the datareception buffer internal phase clocks, to match with the bufferinternal phase clocks, thereby to perform domain crossing.

[0059] According to still another mode of the present invention,there is obtained a memory module having a plurality of memorycircuits and a buffer, wherein a command/address signal istransmitted from the buffer to the plurality of memory circuits,and data signals following the command/address signal aretransmitted/received between the buffer and the plurality of memorycircuits, characterized in that the data signals aretransmitted/received between the plurality of memory circuits andthe buffer synchronously with data phase signals transmitted ontothe same signal line alternately from the memory circuits and thebuffer, and the buffer has means for outputting a control signalfor defining a transmission time of the data phase signal in eachof the memory circuits and the buffer.

BRIEF DESCRIPTION OF THE DRAWINGS:

[0060] FIG. 1 is a block diagram for explaining a memory systemaccording to a first preferred embodiment of the presentinvention;

[0061] FIG. 2 is a schematic stereoscopic wiring diagram forexplaining an actual configuration of the memory system shown inFIG. 1;

[0062] FIG. 3 is a sectional view for explaining the wiring of thememory system shown in FIGS. 1 and 2 more specifically;

[0063] FIG. 4 is a block diagram showing a memory system accordingto a second preferred embodiment of the present invention;

[0064] FIG. 5 is a schematic stereoscopic wiring diagram showingthe memory system shown in FIG. 4;

[0065] FIG. 6 is a block diagram showing a memory system accordingto a third preferred embodiment of the present invention;

[0066] FIG. 7 is a block diagram showing a first modification ofthe memory system according to the third preferred embodiment ofthe present invention;

[0067] FIG. 8 is a block diagram showing a second modification ofthe memory system according to the third preferred embodiment ofthe present invention;

[0068] FIG. 9 is a block diagram showing a third modification ofthe memory system according to the third preferred embodiment ofthe present invention;

[0069] FIG. 10 is a block diagram showing a fourth modification ofthe memory system according to the third preferred embodiment ofthe present invention;

[0070] FIG. 11 is a block diagram for explaining a transmissionsystem between a memory controller and a buffer in the first tothird preferred embodiments of the present invention;

[0071] FIG. 12 is a time chart for explaining an operation of thetransmission system shown in FIG. 11;

[0072] FIG. 13 is a time chart for explaining an operation, uponwriting, of the transmission system shown in FIG. 11;

[0073] FIG. 14 is a time chart for explaining an operation, uponreading, of the transmission system shown in FIG. 11;

[0074] FIG. 15 is a time chart for explaining an operation,associated with a command/address signal, of the transmissionsystem shown in FIG. 11;

[0075] FIG. 16 is a block diagram for explaining a transmissionsystem between a buffer and a DRAM, which is used in the memorysystems according to the first to third preferred embodiments ofthe present invention;

[0076] FIG. 17A is a time chart for explaining a write operation inthe transmission system of FIG. 16;

[0077] FIG. 17B is a time chart for explaining a read operation inthe transmission system of FIG. 16;

[0078] FIG. 18 is a block diagram for explaining a transmissionsystem of the present invention that enables speedup of thetransmission system explained with reference to FIG. 17;

[0079] FIG. 19 is a circuit diagram showing configurations ofdriver portions of a buffer and a DRAM employing the transmissionsystem of FIG. 18;

[0080] FIG. 20 is a circuit diagram showing other configurations ofdriver portions of a buffer and DRAMs employing the transmissionsystem of FIG. 18;

[0081] FIG. 21A is a time chart for explaining a write operationwhen the transmission system of FIG. 20 is employed;

[0082] FIG. 21B is a time chart for explaining a read operationwhen the transmission system of FIG. 20 is employed;

[0083] FIG. 22 is a time chart for schematically explaining atiming relationship among signals in the transmission system ofFIG. 18;

[0084] FIG. 23 is a block diagram for explaining a configuration ofa DRAM that can realize the transmission system shown in FIG.18;

[0085] FIG. 24 is a block diagram for explaining a configuration ofa buffer that can realize the transmission system shown in FIG.18;

[0086] FIG. 25 is a timing chart for explaining a timingrelationship upon the start of operation in the DRAM shown in FIG.23;

[0087] FIG. 26 is a timing chart for explaining a timingrelationship during a normal operation in the DRAM shown in FIG.23;

[0088] FIG. 27 is a time chart for explaining a timing relationshipupon reading in the buffer shown in FIG. 24;

[0089] FIG. 28 is a block diagram showing an example of a DRAM thatcan realize a transmission system according to the presentinvention;

[0090] FIG. 29 is a block diagram of a buffer that can performtransmission/reception of a signal relative to the DRAM shown inFIG. 28;

[0091] FIG. 30 is a time chart for explaining an operation of theDRAM shown in FIG. 28;

[0092] FIG. 31 is a block diagram for explaining a modification ofa transmission system between a buffer and a DRAM;

[0093] FIG. 32 is a timing chart for explaining an operation, uponreading, of the DRAM shown in FIG. 31;

[0094] FIG. 33 is a timing chart for explaining an operation, uponwriting, of the DRAM shown in FIG. 31;

[0095] FIG. 34 is a block diagram for concretely explaining aconfiguration of the DRAM shown in FIG. 31;

[0096] FIG. 35 is a block diagram for concretely explaining aconfiguration of the buffer shown in FIG. 31;

[0097] FIG. 36 is a timing chart for explaining a timingrelationship in the DRAM and the buffer shown in FIGS. 34 and35;

[0098] FIG. 37 is a timing chart for explaining an operation of theDRAM shown in FIG. 34;

[0099] FIG. 38 is a timing chart for explaining an operation of thebuffer shown in FIG. 35;

[0100] FIG. 39 is a block diagram showing another example of a DRAMapplicable to the transmission system shown in FIG. 31;

[0101] FIG. 40 is a block diagram showing an example of a bufferthat can cooperatively work with the DRAM shown in FIG. 39;

[0102] FIG. 41 is a block diagram for explaining a memory moduleaccording to an example of the present invention;

[0103] FIG. 42 is a block diagram for explaining a DRAM that isused in a memory module according to a first example of the presentinvention;

[0104] FIG. 43 is a block diagram for concretely explaining adomain crossing circuit in the DRAM shown in FIG. 42;

[0105] FIG. 44 is a block diagram for explaining a buffer formingthe memory module according to the first example cooperatively withthe DRAM shown in FIG. 43;

[0106] FIG. 45 is a block diagram showing a domain crossing circuitin the buffer shown in FIG. 44;

[0107] FIG. 46 is a timing chart for explaining write operations ofthe buffer and the near-end DRAM that are used in the memory systemshown in FIGS. 42 and 44;

[0108] FIG. 47 is a timing chart for explaining write operations ofthe buffer and the far-end DRAM that are used in the memory systemshown in FIGS. 42 and 44;

[0109] FIG. 48 is a time chart for explaining a read operationbetween the far-end DRAM and the buffer;

[0110] FIG. 49 is a timing chart for explaining an operation of thebuffer upon reading;

[0111] FIG. 50 is a timing chart for explaining an operation of thebuffer when reading out read data from the near-end and far-endDRAMs;

[0112] FIG. 51 is a block diagram showing a DRAM that is used in amemory system according to a second example of the presentinvention;

[0113] FIG. 52 is a block diagram showing a concrete configurationof a domain crossing circuit used in the DRAM shown in FIG. 51;

[0114] FIG. 53 is a block diagram showing a buffer forming thesecond example of the present invention cooperatively with the DRAMshown in FIG. 51;

[0115] FIG. 54 is a block diagram showing a concrete configurationof a domain crossing circuit used in the buffer shown in FIG.53;

[0116] FIG. 55 is a timing chart for explaining a write operationbetween the buffer and the near-end DRAM in the second example;

[0117] FIG. 56 is a timing chart for explaining a write operationbetween the buffer and the far-end DRAM in the second example;

[0118] FIG. 57 is a timing chart for explaining a read operationbetween the buffer and the far-end DRAM in the second example;

[0119] FIG. 58 is a timing chart for explaining an operation of thebuffer when processing read data signals from the near-end andfar-end DRAMs;

[0120] FIG. 59 is a block diagram for explaining a memory systemaccording to a third example of the present invention;

[0121] FIG. 60 is a block diagram showing a configuration of a DRAMthat is used in the example shown in FIG. 59;

[0122] FIG. 61 is a block diagram showing a configuration of abuffer used in the third example;

[0123] FIG. 62 is a timing chart for explaining an operation in thethird example;

[0124] FIG. 63 is a timing chart for explaining a case wherein anoperation during initialization of the DRAM and an operation duringa normal operation thereof differ from each other in the thirdexample;

[0125] FIG. 64 is a block diagram for explaining a memory systemaccording to a fourth example of the present invention;

[0126] FIG. 65 is a time chart for explaining a write operation inthe memory system shown in FIG. 64;

[0127] FIG. 66 is a time chart for explaining a read operation inthe memory system shown in FIG. 64;

[0128] FIG. 67 is a block diagram for explaining a memory systemaccording to a fifth example of the present invention;

[0129] FIG. 68 is a time chart for explaining a write operation ofa first DQ channel portion in the memory system shown in FIG.67;

[0130] FIG. 69 is a time chart for explaining a read operation ofthe first DQ channel portion;

[0131] FIG. 70 is a time chart for explaining a write operation ofa second DQ channel portion in the memory system shown in FIG. 67;and

[0132] FIG. 71 is a time chart for explaining a read operation ofthe second DQ channel portion.

DESCRIPTION OF THE PREFERRED EMBODIMENT:

[0133] Referring to FIGS. 1 and 2, there are respectively shown awiring diagram and a stereoscopic diagram of a memory systemaccording to a first preferred embodiment of the present invention.Further, FIG. 3 is a partial sectional view of the memory systemfor explaining the wiring at a portion of FIGS. 1 and 2 indetail.

[0134] As seen from the figures, the memory system according to thefirst preferred embodiment of the present invention comprises amemory controller 101 and a clock generator 102 (FIG. 1) that aremounted on a mother board 100. Further, on the mother board 100, aplurality of memory modules 103 (four memory modules 103a, 103b,103c, and 103d in FIGS. 2 and 3) are mounted via module connectors104 (FIG. 3).

[0135] Each memory module 103 (subscript omitted) is provided on amodule board thereof with a buffer 105 and, as shown in FIGS. 1 and2, a plurality of DRAMs 110. In the shown example, each memorymodule 103 has one buffer 105, and the memory controller 101 andthe buffers 105 are connected together via data wiring (DQ) 111,command/address wiring (Cmd/Add) 112, and clock wiring (CLK/CLKB)113. As clear from this, the data wiring 111 shown in FIGS. 1 and 2is directly connected to the memory controller 101 via the buffers105, i.e. not connected to the respective DRAMs 110.

[0136] As shown in FIG. 3, the data wiring 111, the command/addresswiring 112, and the clock wiring (CLK/CLKB) 113 are connected fromthe memory controller 101 to the buffer 105 of the memory module103a, then connected therefrom to the buffer 105 of the memorymodule 103b of the next stage. Likewise, these wirings areconnected to the buffers 105 of the subsequent memory modules 103cand 103d in order and terminated at their termination ends withterminating resistances, thereby forming a daisy chain. In otherwords, the wirings such as the data wiring 111 are connected to thebuffers 105 between the memory controller 101 and the memory module103a, between the memory modules 103a and 103b, between the memorymodules 103b and 103c, and between the memory modules 103c and103d, and further, connected point-to-point relative to the buffers105 of the prior and subsequent stages in cascade.

[0137] As shown in FIG. 2, the data wiring (DQ) 111, thecommand/address wiring (Cmd/Add) 112, and the clock wiring 113 canbe respectively parceled into wiring portions on the mother boardand module wiring portions in the memory modules. Further, in theshown memory system, module identification wiring 114 fortransmitting a module identifying signal MID that identifies one ofthe memory modules 103a to 103d is also disposed between the memorycontroller 101 and the buffer 105 and between the buffers 105.

[0138] As shown in FIG. 1, the buffer 105 in each memory module 103and the DRAMs 110 mounted in the subject memory module 103 areconnected together via internal data wiring 111', internalcommand/address wiring 112', and internal clock wiring 113'.Herein, the internal data wiring 111' is connected individually tothe respective DRAMs 110 on the memory module 103, while theinternal command/address wiring 112' and the internal clock wiring113' are respectively provided so as to be common to the DRAMs 110disposed on the left side or the right side of the buffer 105.

[0139] Assuming that the shown DRAM 110 is a DRAM of a x-8configuration that can write and read data per 8 bits, datatransmission/reception is performed on the unit of 8 bits betweeneach DRAM 110 and the buffer 105 in each memory module 103.

[0140] Description will be given about the shown memory system inmore detail. Each of the memory modules 103a and 103b has eightDRAMs 110, wherein four of them are placed on each of the left andright sides of the buffer 105. Further, the data wiring 111 betweenthe memory controller 101 and the buffer 105 and between thebuffers 105 has a 32-bit width. When either one of the memorymodules 103a and 103b is selected by a command/address signal and amodule identifying signal MID, the eight DRAMs 110 on the selectedmemory module 103a, for example, are activated to thereby set thestate wherein data of a 64-bit width in total can betransmitted/received between the eight DRAMs 110 and the buffer105.

[0141] On the other hand, when a DRAM 110 denoted by a broken linein FIGS. 1 and 2 is added to each memory module 103, four DRAMs 110are arranged on the left side of the buffer 105, while five DRAMs110 are arranged on the right side thereof, and the data wiring 111between the memory controller 101 and the buffer 105 and betweenthe buffers 105 has a 36-bit width. In this configuration, wheneither one of the memory modules 103a and 103b is selected by acommand/address signal and a module identifying signal MID, thenine DRAMs 110 on the selected memory module 103a, for example, areactivated to thereby set the state wherein data of a 72-bit widthin total can be transmitted/received between the nine DRAMs 110 andthe buffer 105.

[0142] As described above, it is seen that the eight or nine DRAMs110 on each of the memory modules 103a and 103b form asimultaneously accessible rank in the memory system shown in FIGS.1 and 2.

[0143] Now, referring to FIGS. 1 and 2, further description will begiven about the wiring between the memory controller 101 and thememory module 103a and the wiring between the adjacent memorymodules 103. First, the data wiring 111 will be described. Althoughdata of a 64-bit or 72-bit width are transmitted/received via theinternal wiring 111' between the buffer 105 and the DRAMs 110, thedata wiring 111 between the memory controller 101 and the buffer105 and between the buffers 105 has a 32-bit width or a 36-bitwidth as shown in FIGS. 1 and 2.

[0144] This means that a data signal, multiplexed or compressedinto packets, is transmitted/received on the data wiring 111 at atransmission speed higher than a data frequency, i.e. an operationspeed, of the DRAM 110. In the shown example, data is transferredon the data wiring 111 at a speed that is n (n is a positiveinteger) times the operation speed of the DRAM 110. Accordingly,when compressed into packets, the number of data lines is reducedto about 1/n (not necessarily 1/n because there is actually anindivisible case or the like).

[0145] Like the data wiring 111, the command/address wiring 112 isconnected point-to-point between the memory controller 101 and thememory module 103 and between the adjacent memory modules 103. Inthe command/address wiring 112, a command/address signal istransferred at a speed that is m (m is a positive integer) times acommand/address signal frequency of the DRAM 110 and, whencompressed into packets, the number of signal lines is reduced toabout 1/m (also not necessarily 1/m because there is actually anindivisible case or the like).

[0146] The buffer 105 provided on each memory module 103 has afunction of receiving a data signal or a command/address signalfrom the memory controller 101 or the memory module 103 of theprior stage and encoding packets of the data or command/addresssignal to provide the number of signals corresponding to the DRAMson the subject memory module 103. Further, the buffer 105 has afunction of dividing a frequency of the encoded data orcommand/address signals into 1/n or 1/m times the frequency andsending them to the DRAMs 110.

[0147] Furthermore, the buffer 105 also has a function oftransferring or transmitting a command/address signal to thecascade-connected memory module 103 of the next stage, a functionof bidirectionally transmitting/receiving a data signal relative tothe next-stage memory module, and a function of identifying amodule identifying signal MID representing a packet destination ofa data or command/address signal. Inasmuch as the functions ofdividing, identification, etc. in the buffer 105 can be easilyrealized using the usual techniques, details thereof are not givenhere. In any case, the respective wirings on the memory modules 103are connected with wiring layout having only such branching thatcan be electrically ignored.

[0148] Now, referring to FIG. 2, description will be given abouttransmission speeds in the respective wirings. First, it is assumedthat the DRAMs 110 on each memory module 103 are SDRAMs and employthe DDR (Double Data Rate) system that performs input/output ofdata synchronously with both leading and trailing edges of a clock.Further, assuming that an internal clock frequency of 666 MHz isgiven to the internal clock wiring 113' between the buffer 105 andthe DRAMs 110 in each memory module 103, data is transferred in theinternal data wiring 111' at a data transmission speed of 1.33Gbps, i.e. at a data frequency of 1.33 GHz, and a command/addresssignal of 666 Mbps is supplied from the buffer 105 in the internalcommand/address wiring 112'.

[0149] In this example, it is assumed that the clock wiring 113disposed on the mother board 100 is given, from the memorycontroller 101, clocks having a clock frequency of 1.33 GHz that istwice the internal clock frequency. As shown in FIG. 2, the datawiring 111 and the command/address wiring 112 are fed with data andcommand/address signals at a transmission speed of 2.66 Gbps thatis twice the clock frequency, while transmission speeds of theinternal data wiring 111' and the internal command/address wiring112' are 1.33 Gbps and 666 Mbps, respectively. Therefore, it isseen that n=2 and m=4 in the shown example.

[0150] As described above, by multiplexing the signals on themother board to implement high-frequency transmission, the numberof the lines on the mother board can be reduced. The data wiring111 can be reduced to 1/2 by duplexing the signal, while thecommand/address wiring 112 can be reduced to 1/4 by quadplexing thesignal. Further, by duplexing data, a memory system with datawiring of a 32-bit width (or data wiring of a 36-bit width) can beoperated as a memory system of a 64-bit (or 72-bit)configuration.

[0151] The memory system shown in FIGS. 1 to 3 requires a layoutconfiguration for inputting/outputting a data signal of a 32-bit or36-bit width from the module connector 104 (FIG. 3) to the buffer105. As described before, the internal data wiring 111' and theinternal clock wiring 113' and command/address wiring 112' on thememory module 103 are connected with the wiring layout having onlyelectrically ignorable branching. However, since the number of theDRAMs connected to the internal data wiring 111' and the number ofthe DRAMs connected to the internal clock wiring 113' andcommand/address wiring 112' differ from each other, it can beconsidered that a difference in signal propagation time caused by adifference in load may be a problem upon high-frequency operation.Further, as clear from FIGS. 1 and 2, inasmuch as the clocks andthe command/address signals are given to all the DRAMs 110 on eachmemory module 103, the total input load is large, and therefore, itcan be considered that a problem may be raised upon high-frequencyoperation.

[0152] Referring to FIGS. 4 and 5, a memory system according to asecond preferred embodiment of the present invention has aconfiguration that can reduce the foregoing problems associatedwith the first preferred embodiment. The shown memory systemdiffers from the memory system according to the first preferredembodiment in that each of memory modules 103a to 103d (FIG. 5) isprovided with two buffers 105a and 105b. Specifically, each of thebuffers 105a and 105b of each of the memory modules 103a and 103bis connected to a plurality of DRAMs 110a arranged on both left andright sides thereof via internal data wiring (DQ) 111', internalcommand/address wiring 112', and internal clock wiring 113'.

[0153] In the shown example, the DRAMs 110a within each memorymodule 103 are individually connected to the buffer 105a or 105bvia the internal data wiring (DQ) 111', and further, commonlyconnected to the left or right side of the buffer 105a or 105b viathe internal command/address wiring 112' and the internal clockwiring 113'.

[0154] Further, like in the first embodiment, the buffers 105a and105b within each memory module 103 are connected to a memorycontroller 101 or the memory module of the next stage via datawirings 111, command/address wirings 112, and clock wirings 113.This configuration is the same as the connection relationship shownin FIG. 3 and, as a result, the buffers 105a and 105b of eachmemory module 103 are connected point-to-point to the buffers 105aand 105b of other memory modules 103. That is, the data wirings111, the command/address wirings 112, and the clock wirings 113 areconnected to the buffers 105a and 105b of the subsequent stages incascade in order, thereby forming daisy chains.

[0155] In the example shown in FIG. 5, x-8 configuration DRAMs 110aeach inputting/outputting data per 8 bits are mounted on eachmemory module 103, and each DRAM 110a performs an input/outputoperation according to clocks having a clock frequency of 666 MHzgiven via the internal clock wiring 113'. As a result, acommand/address signal and data are transmitted in the internalcommand/address wiring 112' and the internal data wiring 111' attransmission speeds of 666 MHz and 1.33 GHz, respectively.

[0156] On the other hand, the memory controller 101 and the buffers105a and 105b of the memory module 103a are connected together viathe data wirings 111, the command/address wirings 112, the clockwirings 113, and module identification wirings 114. Further, thesewirings extend to the buffers 105a and 105b of the memory module103b of the next stage, and are further connected to the buffers105a and 105b of the memory modules 103c and 103d that are shownbehind the memory module 103b in FIG. 5. In this manner, the datawirings 111, along with the command/address wirings 112 and theclock wirings 113, are connected to the two buffers 105a and 105bconcentrically, i.e. in groups.

[0157] In FIG. 5, clocks having a frequency of 1.33 GHz are givenon the clock wirings 113, and a command/address signal and data areinputted/outputted on the command/address wirings 112 and the datawirings 111 at a transmission speed of 2.66 Gbps. Therefore, it isseen that each of the buffers 105a and 105b can produce internalclocks, internal command/address signals, and internal data byconverting the clocks, the command/address signal, and the datafrom the memory controller 101 into two or four parallelsignals.

[0158] In this configuration, by simultaneously operating thebuffers 105a and 105b of each memory module 103, it is possible toconstruct a memory system that inputs/outputs data at a 32-bit or36-bit width, like in the first preferred embodiment. In case ofthe memory system for transmitting/receiving data of a 32-bitwidth, the two x-8 configuration DRAMs 110a are placed on each sideof each of the buffers 105a and 105b. When each memory module 103is selected, the eight DRAMs 110a on each memory module 103 areactivated by both buffers 105a and 105b so that data of a 64-bitwidth can be transmitted/received between the buffers 105a and 105band the eight DRAMs 110a. In the shown example, the memorycontroller 101 and each of the buffers 105a and 105b are connectedby the data wiring 111 of a 16-bit width, and these data wirings111 are also connected to the buffers of the memory modules of thesubsequent stages. As clear from this, multiplexed data istransmitted on the data wirings 111 like in the first preferredembodiment.

[0159] On the other hand, in case of the memory system fortransmitting/receiving data of a 36-bit width, data of a 72-bitwidth can be transmitted/received between the nine DRAMs 110a andthe buffers 105a and 105b on each memory module 103. In the exampleshown in FIG. 5, data of a 40-bit width is transmitted/receivedbetween the buffer 105a and the five DRAMs 110a disposed on bothsides of the buffer 105a, while data of a 32-bit width istransmitted/received between the buffer 105b and the four DRAMs110a disposed on both sides of the buffer 105b.

[0160] In this case, the data wiring 111 between the memorycontroller 101 and the buffer 105 a has a 20-bit width, while thedata wiring 111 between the memory controller 101 and the buffer105b has a 16-bit width and, like in the first preferredembodiment, data and command/address signals that are multiplexed,i.e. compressed into packets, are transmitted/received on the datawirings 111 and the command/address wirings 112, respectively.

[0161] In the shown memory system, the number of the DRAMs 110adriven by each of the buffers 105a and 105b can be reduced to halfas compared with the first preferred embodiment, and therefore, thenumber of lines in each of the buffers 105a and 105b on the memorymodule 103 can be reduced and the wiring length can be shortened.Further, inasmuch as the number of the DRAMs 110a, forming loads,of each of the buffers 105a and 105b can be reduced, a differencein input load at the internal data wiring 111', and the internalcommand/address wiring 112' and the internal clock wiring 113' canbe reduced so that the memory system suitable for high-frequencyoperation can be constructed.

[0162] In the memory system shown in FIG. 4, in case of the memorysystem for transmitting/receiving the data of the 36-bit widthbetween the memory controller 101 and the buffers 105a and 105b, itis readily understood that the DRAM 110a surrounded by a brokenline in FIG. 4 is connected in each memory module 103, which isalso clear from FIG. 5.

[0163] The memory system according to the second preferredembodiment shown in FIGS. 4 and 5 can be applied with variousmodifications. For example, instead of the x-8 configuration DRAMs,x-4 configuration DRAMs each inputting/outputting data per 4 bits,or x-16 configuration DRAMs each transmitting/receiving data per 16bits may be disposed on both sides of the two buffers. Further, thepresent invention is applicable not only to a memory system havingDRAMs arranged on only one side of a module board of each memorymodule, but also to a memory system having DRAMs arranged on bothfront and back sides thereof. Moreover, the present invention islikewise applicable to a system in which a plurality of DRAMsarranged on each memory module are classified into a plurality ofranks.

[0164] In the memory system according to the foregoing preferredembodiment, a command/address signal given to each memory module isgiven individually to a plurality of buffers, and therefore, thenumber of command/address signal pins is increased by a multiple ofthe number of the buffers. However, inasmuch as the command/addresssignal is multiplexed, the increase is not so large.

[0165] Referring to FIG. 6, there is shown one example of a memorysystem according to a third preferred embodiment of the presentinvention. The shown memory system has a configuration that canreduce the number of internal data lines between the moduleconnector 104 (FIG. 3) and a buffer without increasing the numberof buffers in each memory module. Specifically, the memory systemshown in FIG. 6 comprises a memory controller 101 and a pluralityof memory modules 103 (only 103a and 103b are shown in the figure),wherein 16 DRAMs 110 (subscript omitted) are mounted on the frontand back sides of each memory module 103. It is assumed that theshown DRAM 110 is a x-8 configuration DRAM that performs write/readper 8 bits. At the centers of the memory modules 103a and 103b,buffers 105(11) and 105(21) are disposed, respectively. The buffer105(11) is connected with 16-bit width data wiring (DQ) 111,command/address wiring (Cmd/Add) 112, clock wiring (CLK) 113, andmodule identifying wiring (MID) 114, and the buffer 105(21) islikewise connected with 16-bit width data wiring (DQ) 111,command/address wiring (Cmd/Add) 112, clock wiring (CLK) 113, andmodule identifying wiring (MID) 114. These wirings of each of thebuffers 105(11) and 105(21) are connected to buffers of non-shownmemory modules to thereby form a daisy chain.

[0166] In this embodiment, the total 32 DRAMs 110 of the two memorymodules 103a and 103b are classified into four groups eachincluding eight DRAMs, which operate as ranks 1 to 4. In thisconnection, wiring from the buffer 105(11), 105(21) to the DRAMs110 in the memory module 103a, 103b is such that the wiring iscommon to the corresponding DRAMs 110 on the front and back sidesof the memory module 103a, 103b and connected together through viaswithin the memory module 103a, 103b, and connected to the same DQterminal of the buffer 105(11), 105(21). Specifically, the DRAMs110 used in the rank 1 and the rank 3 are located in correspondingpositions on the front and back sides of each of the memory modules103a and 103b, while the DRAMs 110 used in the rank 2 and the rank4 are likewise located in corresponding positions on the front andback sides of each of the memory modules 103a and 103b, and theDRAMs of the same rank are activated by the use of address bits forselecting the rank. Taking this into consideration, in FIG. 6, theDRAMs 110 belonging to the rank 1 are assigned a subscript r1 and,likewise, the DRAMs 110 of the ranks 2 to 4 are featured by r2 tor4.

[0167] In this configuration, in case of operating the DRAMs 110 ofthe rank 1, when the four DRAMs 110r1 of each of the memory modules103a and 103b are selected, the state is set wherein data of a32-bit width is transmitted/received via internal data wiring 111'between each of the buffers 105(11) and 105(21) of the memorymodules 103a and 103b and the DRAMs 110r1. In this state, thebuffers 105(11) and 105(21) are respectively connected to thememory controller 101 via the data wirings 111 each having a 16-bitwidth, and therefore, perform transmission/reception of datarelative to the memory controller 101 as 32-bit data wiring intotal.

[0168] In this manner, the four ranks are formed by using the twomemory modules 103a and 103b as a pair, so that the wiring of theranks 1 and 3 can be made common and the wiring of the ranks 2 and4 can be likewise made common in each of the memory modules 103aand 103b to thereby reduce the number of lines in the memorymodules 103a and 103b.

[0169] Here, the memory system shown in FIG. 6 differs from thememory system according to the first preferred embodiment in thateach of the buffers 105(11) and 103(21) is directly connected tothe memory controller 101, and further differs from the memorysystem according to the second preferred embodiment in that thesingle buffer 105(11), 105(21) of the memory module 103a, 103b isconnected via the data wiring 111 of the 16-bit width.

[0170] In the configuration shown in FIG. 6, a chip select signal(CS) is used for identifying the ranks 1 to 4. However, bits foridentifying the ranks 1 to 4 may be added separately.

[0171] Now, description will be given about an operation of thememory system shown in FIG. 6. When one command/address signal isoutputted from the memory controller 101, this command/addresssignal is, in this example, fed to the two memory modules 103a and103b. In this event, it is needless to say that the command/addresssignal is outputted from the memory controller 101 synchronouslywith the clocks. The command/address signal activates the eightDRAMs of the same rank in the two memory modules 103a and 103b, forexample, the DRAMs 110r1 of the rank 1, so that a write/readoperation of data is implemented between the activated eight DRAMs110r1 and the buffers 105(11) and 105(21) in the memory modules103a and 103b. In this case, the four DRAMs 110r1 on the memorymodule 103a are activated so that 32-bit width data can betransmitted/received relative to the buffer 105(11), while the fourDRAMs 110r1 on the memory module 103b are activated so that 32-bitwidth data can be transmitted/received relative to the buffer105(21) likewise.

[0172] Inasmuch as the buffers 105(11) and 105(21) are connected tothe memory controller 101 via the 16-bit width data wirings 111,respectively, multiplexed data is transmitted between the memorycontroller 101 and the buffers 105(11) and 105(21), which is thesame as the foregoing preferred embodiments.

[0173] The buffers 105(11) and 105(21) of the memory modules 103aand 103b may be connected to buffers of non-shown other memorymodules, respectively, to thereby form daisy chains. Therefore, thebuffers of the shown memory system may be expressed by105(12.about.1k) and 105(22.about.2k) (k is a positive integerequal to 3 or greater). As clear from this, memory modules of theshown memory system may be increased if necessary.

[0174] In the memory system according to the third preferredembodiment shown in FIG. 6, if the same DRAMs 110 as those in thememory system according to the first preferred embodiment areprovided, the number of ranks of the DRAMs 110 is increased fromtwo to four. There is a merit in this embodiment that since thewiring in each memory module can be made common by providing therank configuration of the DRAMs in each memory module, the degreeof freedom of layout on each memory module 103 can be enhanced, andfurther, the number of buffer chips can be reduced as compared withthe second preferred embodiment. Further, as shown in FIG. 6,inasmuch as data from the memory controller 101 to the memorymodule 103b is given to the buffer 105(21) of the memory module103b directly, i.e. without passing through another buffer, a logicdelay due to the buffer can be reduced as compared with the memorysystems according to the first and second preferred embodiments inwhich data is transmitted/received via the two buffers 105.

[0175] Referring to FIG. 7, there is shown a modification of thememory system according to the third preferred embodiment of thepresent invention. This memory system comprises only two memorymodules 103a and 103b, and is a memory system that does not takeinto consideration the increase of memory modules. In this example,buffers 105 respectively provided in the memory modules 103a and103b do not form a daisy chain relative to other memory modules,but are terminated with terminating resistances. In other words, inthe shown example, inasmuch as there are no other memory modulesthat are connected in cascade, the buffers of the memory modules103a and 103b are represented by reference numerals 105(1) and105(2), respectively, in FIG. 7. On the other hand, 16 DRAMs 110provided on the front and back sides of each of the memory modules103a and 103b are grouped into four ranks, and wiring of the rank 1and the rank 3 is made common and wiring of the rank 2 and the rank4 is likewise made common in each of the memory modules 103a and103b, which is the same as FIG. 6.

[0176] Referring to FIG. 8, there is shown another modification ofthe memory system according to the third preferred embodiment ofthe present invention. This modification comprises four memorymodules 103a to 103d each having a single buffer 105, and thebuffers 105(1) to 105(4) (buffers 105(3) and 105(4) are not shown)of these memory modules are directly connected to the memorycontroller 101, which differs from the memory systems of FIGS. 6and 7. Accordingly, each buffer 105 of the memory system shown inFIG. 8 is connected to the memory controller 101 with the number ofdata lines corresponding to a quarter of a 32-bit width, and x-8configuration DRAMs 110 on each of the memory modules 103a to 103dare classified into eight ranks, thereby improving the degree offreedom of layout of each of the memory modules 103a to 103d.

[0177] As described above, in this embodiment, the 8-rankconfiguration is formed by using the four memory modules 103a to103d as a set. The 16 DRAMs 110 are mounted in each of the memorymodules 103a to 103d, wherein the four DRAMs arranged on the righton the front side of each memory module are classified into theranks 1 to 4, the four DRAMs arranged on the right on the back sideof each memory module are classified into the ranks 5 to 8, thefour DRAMs arranged on the left on the front side of each memorymodule are classified into the ranks 1 to 4, and the four DRAMsarranged on the left on the back side of each memory module areclassified into the ranks 5 to 8. The rank 1 and the rank 5, therank 2 and the rank 6, the rank 3 and the rank 7, and the rank 4and the rank 8 are located in corresponding positions on the frontand back sides of each memory module, and wiring from each of thebuffers 105(1) to 105(4) to the DRAMs of those ranks is made commonand connected through vias. The memory system shown in FIG. 8differs from that shown in FIG. 6 in that each of data wirings tothe memory modules 103(a) to 103(d) is 8 bits in the memory systemof FIG. 8 to thereby form 32-bit data wiring over the whole memorysystem.

[0178] As described before, the DRAMs 110 of each of the memorymodules 103a and 103b are classified into the eight ranks and, forclarifying this, the DRAMs 110 of the ranks 1 to 8 are representedby reference symbols 110r1 to 110r8, respectively, in FIG. 8.

[0179] In this configuration, when an address signal is given fromthe memory controller 101 as a command/address signal (Cmd/Add),the two DRAMs of the same rank in each of the memory modules 103ato 103d, for example, the two DRAMs 110r1 of the rank 1 in eachmemory module, are activated, and therefore, the state is setwherein 16-bit width data can be transmitted/received relative toeach of the buffers 105(1) to 105(4) so that 64-bit width data intotal can be transmitted/received over the four buffers 105(1) to105(4). As shown in the figure, data wiring 111 of each of thememory modules 103a to 103d is 8 bits, and multiplexed data istransmitted/received between the memory controller 101 and each ofthe buffers 105(1) to 105(4) on the data line 111 of each of thememory modules 103a to 103d.

[0180] Referring to FIG. 9, there is shown still anothermodification of the memory system according to the third preferredembodiment of the present invention, wherein a 2-rank memory systemis formed by using two memory modules 103a and 103b as a pair. Thememory system of FIG. 9 differs from that of FIG. 6 in that 16DRAMs disposed on the front side of the two memory modules 103a and103b form a rank 1, while 16 DRAMs on the back side thereof form arank 2, and each DRAM 110 is a x-4 configuration DRAM. Further, inFIG. 9, the eight DRAMs 110 mounted on the front side of each ofthe memory modules 103a and 103b form the rank 1, while the eightDRAMs 110 mounted on the back side thereof form the rank 2. In thisconnection, in FIG. 9, the 16 DRAMs 110 belonging to the rank 1 andarranged in the memory modules 103a and 103b are denoted byreference symbol 110r1, while the 16 DRAMs 110 belonging to therank 2 are denoted by reference symbol 110r2. Further, the DRAMs110r1 and 110r2 of the ranks 1 and 2 arranged on the front and backsides of each of the memory modules 103a and 103b are commonlyconnected to each other via internal data wiring of a 4-bitwidth.

[0181] On the other hand, a buffer 105 of each of the memorymodules 103a and 103b is connected to the memory controller 101 via16-bit width data wiring 111, and multiplexed data is transmittedon each of the data wirings 111, which is the same as the otherexamples. Even with this configuration, like the memory systemshown in FIG. 6, 32-bit width data is transmitted between the eightDRAMs 110r1, 110r2 of the memory module 103a, 103b and the buffer105, and further, multiplexed data of a 16-bit width is transmittedbetween each buffer 105 and the memory controller 101.

[0182] Referring to FIG. 10, there is shown an example having a36-bit bus width with parity bits, as still another modification ofthe memory system according to the third preferred embodiment ofthe present invention.

[0183] This example differs from the memory system shown in FIG. 9in that nine x-4 configuration DRAMs 110 are mounted on each of thefront and back sides of each of memory modules 103a and 103b, anddata wiring 111 between a buffer 105 of each of the memory modules103a and 103b and the memory controller 101 has an 18-bit width.Specifically, in each of the memory modules 103a and 103b shown inFIG. 10, four DRAMs 110 are arranged on the left on each of thefront and back sides of the buffer 105, while five DRAMs 110 arearranged on the right of each of the front and back sides of thebuffer 105. Here, it is assumed that the DRAM 110 placed on therightmost on each of the front and back sides of each of the memorymodules 103a and 103b is used as a DRAM for parity.

[0184] Like FIG. 9, this example is also a 2-rank memory systemusing the two memory modules 103a and 103b as a pair. Further, the18 DRAMs 110 arranged on the front side of the two memory modules103a and 103b form a rank 1, while the 18 DRAMs 110 arranged on theback side thereof form a rank 2. In this connection, the DRAMs ofthe ranks 1 and 2 are denoted by reference symbols 110r1 and 110r2,respectively. Further, internal data wiring of the DRAMs 110r1 and110r2 of the ranks 1 and 2 arranged on the front and back sides ofeach memory module is common, which is also the same as FIG. 9.

[0185] Further, the buffer 105 of each of the memory modules 103aand 103b is connected to the memory controller 101 via data wiring111 corresponding to an 18-bit width, and is connected to buffersof non-shown memory modules in cascade to thereby form a daisychain.

[0186] In this configuration, multiplexed data with parity istransmitted/received between the memory controller 101 and thememory module 103a or 103b.

[0187] Comparison will be made between the first and secondpreferred embodiments and the third preferred embodiment. In thefirst and second preferred embodiments, sincetransmission/reception of data between the DRAMs on thecascade-connected second memory module and the memory controller iscarried out via two buffer chips, a logic delay necessary forreception/transmission processing at the buffer chips becomes twicethe third preferred embodiment. On the other hand, in the thirdpreferred embodiment, although there is the merit of reducing thenumber of buffers to be passed through, it is necessary to increasethe number of ranks of the DRAMs on the memory module.

[0188] Referring to FIG. 11, more detailed description will begiven about the signal transmission system between the memorycontroller (MC) 101 and each memory module 103 in the foregoingmemory systems. In the shown example, it is assumed for simplifyingthe description that buffers 105a and 105b of memory modules 103aand 103b are connected in cascade. In this system, the memorycontroller 101 transmits a command/address signal (CA)synchronously with a clock signal, and these command/address signal(CA) and the clock signal are received at the buffers 105a and 105bof the memory modules 103a and 103b in order.

[0189] On the other hand, data (DQ) signals aretransmitted/received at the buffers 105a and 105b and the memorycontroller 101 synchronously with a plurality of pairs ofbidirectional clock signals (complementary) CLK and CLKB.Specifically, when writing data into the DRAMs of the memorymodules 103a and 103b from the memory controller 101, the data istransmitted to the buffers 105a and 105b synchronously with clocksoutputted from the memory controller 101, while, when reading datafrom the DRAMs of the memory modules 103a and 103b, the buffers105a and 105b of the memory modules 103a and 103b produce clocksfrom internal clocks of the DRAMs and output read data from theDRAMs to the memory controller 101 synchronously with the producedclocks. Upon packet transmission of a command/address signal and adata signal, a module identifying signal MID is transmitted fromthe memory controller 101 simultaneously with these command/addresssignal and data signal, and the buffers 105a and 105b identifyeffective head data of the signals and a reception/transmissiondestination memory module using the signal MID.

[0190] Referring to FIG. 12, there is shown a timing relationshipin the system shown in FIG. 11. In the shown example, clocks havinga frequency of 1.33 GHz (i.e. period of 0.75 ns) are produced fromthe memory controller (MC) 101 (see the first line in FIG. 12) and,synchronously with leading and trailing edges of the clocks, datais transmitted from the memory controller (MC) 101 to the buffers(see the third line). As a result, the data is transmitted to thebuffers 105a and 105b from the memory controller (MC) 101 at atransmission speed of 2.66 Gbps.

[0191] On the other hand, internal clocks having a frequency of 666MHz (period of 1.5 ns) are produced from the buffers 105a and 105brelative to the DRAMs (see the second line) and, with a lapse of abuffer internal latency time, the data received at the buffers arewritten into the DRAMs at a transmission speed of 1.33 Gbpssynchronously with leading and trailing edges of the internalclocks (see the fourth line).

[0192] Then, synchronously with leading and trailing edges of theclocks having a frequency of 1.33 GHz, a command/address signal(CA) is outputted to the buffers 105a and 105b from the memorycontroller (MC) 101 (see the fifth line). After a lapse of a bufferinternal latency time, the command/address signal (CA) is outputtedto the DRAMs from the buffers synchronously with leading edges ofthe internal clocks (see the sixth line). Therefore, thecommand/address signal is outputted from the memory controller (MC)to the buffers 105a and 105b at a transmission speed of 2.66 Gbpsand outputted from the buffers to the DRAMs at a transmission speedof 666 Mbps. Further, a module identifying signal MID is outputtedfrom the memory controller (MC) to the buffers at a transmissionspeed of 2.66 Gbps synchronously with leading and trailing edges ofthe clocks of 1.33 GHz.

[0193] As clear from this, between the memory controller (MC) 101and the buffers 105a and 105b, the data is transferred at afrequency twice the data frequency of the DRAMs, while thecommand/address signal (CA) is transferred at a four-timesfrequency. Therefore, the buffer on each memory module reduces thefrequencies of the data and the command/address signal to 1/2 and1/4, respectively, by the use of a frequency divider or the like,and transmits them to the DRAMs.

[0194] Here, it is assumed that the memory system processes 8-bitcontinuous data (burst). Specifically, it is assumed that 16-bitcontinuous data is outputted on a 32-bit data bus at a transmissionspeed of 2.66 Gbps from the memory controller (MC) 101 to thebuffers, and each buffer outputs the 16-bit continuous dataalternately to two DQ pins of the DRAMs as 8-bit continuous data ata transmission speed of 1.33 Gbps.

[0195] Further, the command/address signal is outputted at atransmission speed of 2.66 Gbps from the memory controller (MC) tothe buffers, and 4-bit data, for example, of one command/addresssignal line is distributed to four command/address signal lines atthe buffer, thereby to be fed to the DRAMs at a transmission speedof 666 Mbps.

[0196] Now, further detailed description will be given about theforegoing operation by dividing it into data write and readoperations, and a command/address signal transfer operation. FIG.13 shows a data write operation from the memory controller (MC) tothe DRAMs. As described above, the memory controller (MC) 101outputs the clocks of 1.33 GHz to the buffers 105 (see the firstline). Synchronously with the clocks, a module identifying signalMID and data DQ0m are outputted from the memory controller (MC) 101(see the third and fourth lines).

[0197] Here, the module identifying signal MID includes aneffective data head identifying signal and a destination address,while the data DQ0m includes two data sequences DQ0 and DQ1 to bedistributed to two DQ pins of the DRAMs. Here, the data sequenceDQ0 becomes continuous 8-bit data DQ00, 10, 20, 30 . . . 70, whilethe data sequence DQ1 becomes continuous 8-bit data DQ01, 11, 21,31 . . . 71. As shown at the fourth line of FIG. 13, in the dataDQ0m, unit data of the data sequences DQ0 and DQ1 are alternatelyplaced synchronously with leading and trailing edges of the clocksshown at the first line. The data DQ0m is outputted from the memorycontroller (MC) 101 to the buffer 105a synchronously with theclocks. Here, when the number of data lines from the memorycontroller (MC) to the buffer is 32 in total, since data is fed totwo DQ terminals of the DRAMs from the respective data lines, thesystem as a whole processes 8-bit continuous data at a 64-bitwidth. When the first-stage buffer 105a judges from the moduleidentifying signal MID that it is not addressed to the memorymodule 103a to which the buffer 105a belongs, the moduleidentifying signal MID is transferred to the next-stage memorymodule 103b along with the data DQ0m (see the third and fourthlines).

[0198] Then, as shown at the second line, the buffer 105a in thememory module 103a produces internal clocks of 666 MHz by dividingthe clocks of 1.33 GHz to half, and outputs them to the DRAMs. Ifthe memory module 103a is designated by the foregoing moduleidentifying signal MID, the shown data DQ0m is, after a lapse of abuffer latency, written into the given DRAMs synchronously with theinternal clocks. In the shown example, as shown at the fifth andsixth lines, the data sequences DQ0 and DQ1 are outputted from thebuffer 105a to the two DRAMs synchronously with leading andtrailing edges of the internal clocks.

[0199] Now, referring to FIG. 14, description will be given aboutan operation when the data DQ0m is read from the DRAMs. In thiscase, it is assumed that the data DQ0m is read from the DRAMs ofthe memory module 103a to the memory controller (MC) 101 via thebuffer 105a. First, the buffer 105a is outputting the internalclocks of 666 MHz to the DRAMs (see the second line in FIG. 14),while outputting the clocks having a frequency of 1.33 GHz to thememory controller (MC) 101 (see the first line). In this state, itis assumed that the data sequences DQ0 and DQ1 are read from two DQterminals of the DRAMs. Here, it is assumed that the data sequencesDQ0 and DQ1 include unit data DOO, 10, 20 . . . 70 and unit dataD01, 11, 21 . . . 71, respectively (see the fifth and sixth lines).These unit data are sent out to the buffer 105a from the two DQterminals synchronously with the internal clocks. The buffer 105aoutputs a module identifying signal MID representing the memorymodule 103a to which the buffer 105a belongs, to the memorycontroller (MC) as an effective data head identifying signal (seethe third line). Subsequently, the buffer 105a alternately combinesthe continuous 8-bit unit data of the data sequences DQ0 and DQ1from the two DQ terminals to multiplex them, and outputs themultiplexed data to the memory controller 101 synchronously withthe clocks between the buffer 105a and the memory controller 101 asthe 16-bit read data DQ0m. In case of a buffer located at a laterstage of the buffer 105a like the buffer 105b, the data DQ0m isgiven to the memory controller (MC) via the buffer 105a of theprior stage.

[0200] As described above, it is seen that the data transmissionspeed and the clock frequency between the memory controller (MC)101 and the buffers 105a and 105b are greater than the datatransmission speed and the clock frequency between the buffers 105aand 105b and the DRAMs. With this configuration, the datawrite/read can be implemented at the transmission speed dependingon the operation speed of the DRAMs by reducing the number of linesbetween the memory controller (MC) 101 and the buffers.

[0201] Further, referring to FIG. 15, there is shown an operationwhen a command/address signal is given to the memory modules fromthe memory controller (MC) 101. As described before, it is assumedthat the clocks having a frequency of 1.33 GHz is fed to thebuffers 105a and 105b from the memory controller (MC) 101 (see thefirst line), the internal clocks of 666 MHz are used between eachbuffer 105 and the DRAMs 110 (see the second line). In this case, amodule identifying signal MID includes a head identifying signaland a destination address signal of a command/address signal CA0m,the head identifying signal and the destination address signal ofthe command/address signal CA0m are outputted from the memorycontroller (MC) 101 synchronously with leading and trailing edgesof the clocks of 1.33 GHz (see the third line), and the signal MIDis transferred to the buffer 105a of the prior-stage memory module103a and also to the buffer 105b of the subsequent-stage memorymodule 103b.

[0202] In this example, simultaneously with the module identifyingsignal MID, address signals A0 to A3 are outputted from the memorycontroller (MC) 101 to the buffer 105a in multiplexed mode as thecommand/address signal CA0m synchronously with leading and trailingedges of the clocks of 1.33 GHz, and subsequently, transferred tothe buffer 105b (see the fourth line). The buffer 105 of the memorymodule 103 designated by the foregoing module identifying signalMID feeds the address signals A0 to A3 to the DRAMs mounted on thedesignated memory module 103 synchronously with the internalclocks. In FIG. 15, although only one of command/address signals isshown, a plurality of command/address signals given to the bufferare respectively converted into four command/address signals, forexample, RAS, CAS, WE, and band address, and residual addresssignals etc. Through this, an operation mode, the DRAMs, and memorycells in the DRAMs within the designated memory module areselected.

[0203] In the foregoing, the description was given mainly about thesignal transmission between the memory controller (MC) 101 and thememory modules 103. However, it is desirable that signaltransmission can be achieved at high speed also between each memorymodule 103 and the DRAMs within the subject memory module 103.

[0204] For this purpose, the present invention proposes a method oftransmitting data at high speed between the buffer 105 and theDRAM. Hereinbelow, description will be given about a case whereinthe data transmission method according to the present invention isapplied to the memory systems according to the foregoing first tothird preferred embodiments of the present invention, but notnecessarily limited thereto.

[0205] Referring to FIG. 16, there are shown the DRAM 110 and thebuffer 105 in the memory module 103 of the foregoing memorysystem.

[0206] In FIG. 16, the DRAM 110 performs datareception/transmission relative to the buffer 105 using data strobesignals DQS (and DQS* as complementary) (hereinbelow, only DQS willbe described). In this case, the data strobe signal DQS is producedsynchronously with clocks and, when bidirectionally transmittingdata DQ, the data strobe signal DQS is transmitted in atransmission direction of the data DQ. For example, whentransmitting the data DQ in a direction from the DRAM 110 to thebuffer 105, the data strobe signal DQS is also outputted from theDRAM 110 to the buffer 105. This also applies to a case whereindata is transmitted from the buffer 105 to the DRAM 110.

[0207] Referring to FIG. 17A, there is shown an operation whenwriting data into the DRAM 110 from the buffer 105 in FIG. 16,while FIG. 17B shows an operation when reading data from the DRAM110. First, as shown in FIG. 17A, in case of data writing, after awrite command (WRT) and an address (Add) are given to the DRAM fromthe buffer, data writing is implemented with a data strobe signalDQS synchronously with leading and trailing edges of the clocks,and this writing operation continues while the strobe signal DQS isgiven. Therefore, subsequently to the production of thecommand/address signal, data is written after a lapse of apredetermined latency time (WL=4 in the figure).

[0208] Further, as shown in FIG. 17B, also in case of data reading,a read command (RED) and an address (Add) are given to the DRAMfrom the buffer, and data reading is implemented with a data strobesignal DQS synchronously with leading and trailing edges of theclocks.

[0209] As described above, when the data strobe signal DQS is used,data is transmitted at the timing matched with the data strobesignal DQS, and received by the data strobe signal DQS.Accordingly, in the transmission/reception system using the datastrobe signal, it is necessary that logics and layout delays of thedata strobe signal DQS and the data DQ be matched with each otherwithin the reception-side device. However, when a delay changes dueto temperature variation or voltage variation, a setup and a holdtime of a signal receivable by the device are deteriorated. Forhigher frequency operation, a shorter setup and hold time arerequired. Therefore, there is a limitation in speedup in the systemwherein the data strobe signal is transmitted bidirectionally.

[0210] For carrying out data transmission/reception between theDRAM 110 and the buffer 105 at higher speed, the present inventionproposes to use, instead of the foregoing data strobe signal DQS, asignal (herein called "data phase signal DPS") that is constantlytransmitted bidirectionally at the timing of a data signal andtransmitted/received at the DRAM 110 and the buffer 105. By usingthe data phase signal DPS that is transmitted/receivedbidirectionally, transmission/reception clocks can be reproducedusing a DLL in each device. Further, when the DLL is used, it ispossible to cancel temperature variation or voltage variation by areplica delay, and further, since clocks can be set to the optimumtiming, data reception is made possible without using a delaylogic. Therefore, a shorter setup and hold time can beachieved.

[0211] Referring to FIG. 18, there is shown a schematicconfiguration of a data transmission system in which datatransmission is performed between the DRAM 110 and the buffer 105using the foregoing data phase signal DPS. As clear from comparisonwith FIG. 16, in the data transmission system shown in FIG. 18, thedata phase signal DPS is, instead of the data strobe signal DQS,transmitted/received bidirectionally between the buffer 105 and theDRAM 110, and the data phase signal DPS is, as a timing signal ofdata DQ transmitted from the buffer 105 or the DRAM 110, fed to theother device. Specifically, when writing data DQ into the DRAM 110from the buffer 105, a write data phase signal DPS is fed to theDRAM 110 from the buffer 105 along with write data DQ atpredetermined write timing, while, when reading data DQ from theDRAM 110, a read data phase signal DPS produced at timing differentfrom the foregoing write timing is fed to the buffer 105 from theDRAM 110 along with read data DQ.

[0212] By identifying the write timing and the read timing, theDRAM 110 and the buffer 105 respectively extract the write dataphase signal and the read data phase signal (DPS), and performwriting and reading of the data DQ using the extracted write dataphase signal and read data phase signal (DPS). As clear from this,the buffer 105 and the DRAM 110 are provided with, in addition tothe foregoing DLLs, circuits for identifying the timings of thewrite data phase signal and the read data phase signal (DPS).

[0213] Referring to FIG. 19, there are shown driver circuits andreceiver circuits (i.e. transmission/reception circuits) of abuffer 105 and a DRAM 110 that are used when transmitting/receivinga data phase signal DPS between the buffer 105 and the DRAM 110 ina 1-rank configuration. As shown in the figure, each of the driversof the buffer 105 and the DRAM 110 is provided with an open-drainN-channel MOS transistor. The drain of the N-channel MOS transistorof the DRAM 110 is connected with a variable resistance as aterminating resistance, while the drain of the N-channel MOStransistor of the buffer 105 is connected with a fixed resistanceas a terminating resistance. When the variable resistance isconnected, a resistance value can be adjusted by the rankconfiguration of the DRAM side. Although the terminating resistanceis provided within each of the DRAM 110 and the buffer 105, it isreadily understood that it may be provided outside the device. Asignal line for data phase signal DPS transmission connected to thedrains of both transistors of the DRAM 110 and the buffer 105 isconnected to internal circuits of the DRAM 110 and the buffer 105via amplifiers, respectively.

[0214] In the configuration shown in FIG. 19, a timing signal isgiven to the gate of the N-channel MOS transistor of the buffer 105at predetermined timing and period to thereby turn ON/OFF theN-channel MOS transistor of the buffer 105, so that a write dataphase signal DPS is fed to the DRAM 110 from the buffer 105 andalso to the inside of the buffer 105. On the other hand, a timingsignal having a phase different from that of the timing signal ofthe buffer 105 while produced at the same period is given to thegate of the N-channel MOS transistor of the DRAM 110 to therebyturn ON/OFF the N-channel MOS transistor of the DRAM 110, so that aread data phase signal DPS is fed to the buffer 105 from the DRAM110 and also to the inside of the DRAM 110. As shown in the figure,since the driver in each of the DRAM 110 and the buffer 105 is inopen-drain mode, a bus is in a so-called wired OR configuration,and further, since the data phase signals DPS from the DRAM 110 andthe buffer 105 are outputted at the different timings, even if bothsignals are outputted on the same signal line, there is nopossibility of collision therebetween.

[0215] Referring to FIG. 20, there are shown driver circuits fordata phase signal DPS transmission/reception in a case wherein twoDRAMs 110 in a 2-rank configuration are connected to a buffer 105.As clear from the figure, the configuration of FIG. 20 differs fromthat of FIG. 19 in that the drivers of the two DRAMs 110 areconnected to a single signal line of data phase signal DPS, whilethe configuration in each DRAM 110 is the same. A variableresistance is connected to the drain of an N-channel MOS transistorin each DRAM 110 and, in this example, is adjusted to a resistancevalue suitable for the 2-rank configuration of the DRAMs 110.

[0216] Referring to FIGS. 21A and 21B along with FIG. 18,description will be given about an operation when writing data DQ(i.e. write operation) relative to the DRAM 110, and an operationwhen reading data DQ (i.e. read operation) from the DRAM 110. Asshown in FIG. 21A, upon write operation, the buffer 105 feeds awrite command (WRT) and an address signal (Add) to the DRAM 110synchronously with clocks. In this event, a write data phase signalWDPS is transmitted to the DRAM 110 from the buffer 105 as a dataphase signal DPS (see the fourth line). The shown write data phasesignal WDPS is featured by the timing of a leading edge (rise) ofeach of pulses in a pulse stream having a frequency that is 1/4times the clocks.

[0217] On the other hand, a read data phase signal RDPS istransmitted on the same signal line in multiplexed mode from theDRAM 110 to the buffer 105 at the timing that avoids collision withthe write data phase signal WDPS (here, the timing shifted by twoclocks). As shown at the fourth line in FIG. 21B, like the writedata phase signal WDPS, the read data phase signal RDPS is featuredby the timings of leading edges (rise) of a pulse stream having afrequency 1/4 times the clocks, and the timings thereof occurbetween the timings of the write data phase signal WDPS. In thismanner, by deviating the timing between the write data phase signalWDPS and the read data phase signal RDPS, both signals areprevented from collision therebetween on the single signal line. Inthe shown example, the timing between the write data phase signalWDPS and the read data phase signal RDPS is shifted by two clocks.However, it is needless to say that the timing is not limitedthereto as long as collision of both signals can be avoided.

[0218] Referring further to FIG. 21A, the phases of the clocks andthe write data phase signal (WDPS) agree with each other at thebuffer 105 in the write operation from the buffer 105, while thephase of the read data phase signal (RDPS) transmitted from theDRAM does not agree therewith. The data DQ is written after a lapseof a write latency time (WL=4) such that edges of rise (leadingedge) and fall (trailing edge) of the clocks are placed at thecenter of a signal effective width.

[0219] Upon the read operation shown in FIG. 21B, the DRAM 110reproduces the clocks in the DRAM 110 from the read data phasesignal (RDPS). Matching with the timing of the reproduced clocks,the data DQ is transmitted to the buffer 105 from the DRAM 110. Inthe shown example, the timing of the data coincides with the clockedge. However, the center of the effective width may be matchedwith the clock edge.

[0220] In the foregoing example, the DRAM 110 and the buffer 105constantly transmit the data phase signals DPS bidirectionally onthe same signal line during a normal operation, i.e. during anoperation other than a power save mode. Further, the drivers of theDRAM 110 and the buffer 105 are operated at the timings shifted bytwo clocks and, as shown in FIGS. 19 and 20, the open-drain mode isemployed. Accordingly, the bus is in the so-called wired ORconfiguration, and therefore, there is no possibility of busfight.

[0221] Referring to FIGS. 21A and 21B, the description was givenabout the timing relationship between the clocks and the write andread data phase signals WDPS and RDPS upon writing and reading, andthe timing relationship among the data, the clocks, and the dataphase signals (WDPS, RDPS). In the DRAM 110 and the buffer 105having received the data phase signals (WDPS, RDPS), it isnecessary to reproduce therein the data transmission/receptionclocks from the data phase signals (WDPS, RDPS).

[0222] Now, referring to FIG. 22, description will be given about aprocedure of reproducing the data reception/transmission clocksinside the DRAM 110 and the buffer 105 from the data phase signalDPS (write or read data phase signal WDPS, RDPS) according to thepresent invention upon the start of operation of the memorysystem.

[0223] First, the buffer 105 is transmitting clocks to the DRAM 110(see the first line). In this example, the buffer 105 produces theclocks having a frequency of 666 MHz. In this state, the buffer 105transmits a write data phase signal WDPS (see the second line)synchronously with the clocks. The shown write data phase signalWDPS is produced by dividing the frequency of the clocks toquarter, and therefore, the write data phase signal WDPS has afrequency of 666/4 MHz (i.e. 1/4 times the clocks), and the writedata phase signal WDPS is inputted into the DRAM 110 with a timedelay (see the third line).

[0224] The DRAM 110 produces, using a DLL provided in the insidethereof, internal clocks as reproduced clocks for determining data(DQ) reception timing, from the write data phase signal WDPS (seethe fourth line). The shown internal clocks have a frequency of 666MHz.

[0225] Further, as shown in FIG. 22, after reproducing the data(DQ) reception clocks as the internal clocks, the DRAM 110 producesa read data phase signal RDPS shown by a solid line, based on thewrite data phase signal WDPS and the internal clocks by shiftingthe internal clocks by two clocks, and transmits the read dataphase signal RDPS to the buffer 105 (see the fifth line). As shownin FIG. 22, the read data phase signal RDPS has a frequency 1/4times the internal clocks, and is produced so as not to collidewith the write data phase signal WDPS shown by a broken line.

[0226] The read data phase signal RDPS is received at the buffer105 with a time delay (see the sixth line), and the buffer 105reproduces data (DQ) reception clocks of 666 MHz for receiving datafrom the DRAM 110 in the buffer 105 (see the seventh line), fromthe received read data phase signal RDPS. The timing chart shown inFIG. 22 conceptually explains the timing relationship between thedata phase signals DPS and the clocks, while, actually, asdescribed later, the DRAM internal clocks for data reception anddata output are produced at the optimum internal timings,respectively. Further, the shown clocks do not necessarily have aperiod 1/4 times that of the data phase signals DPS, and may bemultiphase clocks.

[0227] In any case, a feature of the shown transmission systemresides in that the reception/transmission clocks within the DRAM110 and the buffer 105 are reproduced from the data phase signalsWDPS and RDPS.

[0228] Referring to FIG. 23, description will be given about aconcrete configuration of the DRAM 110 that performs the foregoingoperation. In the figure, only an interface fortransmitting/receiving data phase signals DPS and data (DQ)relative to the buffer 105 is shown, and a memory cell region forwriting and reading the data (DQ) is omitted in FIG. 23.Incidentally, the memory cell region of the DRAM 110 is connectedto a data (DQ) output driver 201 and a data receiver 202 to therebyperform reading and writing of the data (DQ). Further, the shownDRAM 110 is provided with a clock reproduction phase adjusting andfrequency multiplier circuit 205 composed of a DLL. A write dataphase signal WDPS is inputted into the DLL 205, while a read dataphase signal RDPS from the DLL 205 is outputted via a DPS outputdriver 207. As clear from this, it is assumed that the shown DLL205 is provided with a delay line including a plurality of delaycells, a phase detector, an integrator, and a frequencymultiplier.

[0229] Specifically, the DLL 205 is given data phase signals DPSincluding write and read data phase signals WDPS and RDPS, and thedata phase signals DPS are also given to a reception phasecomparing circuit 206 and an output phase comparing circuit 209.The DLL 205 reproduces data reception DRAM internal clocks from thewrite data phase signal WDPS, and produces data reception feedbackclocks. The data reception DRAM internal clocks are given to thedata receiver 202 so as to be used for writing data DQ, while thedata reception feedback clocks are given to a reception replica 208where the clocks are divided to quarter in frequency, so that areplica signal of the received write data phase signal WDPS isoutputted to the reception phase comparing circuit 206. Thereception phase comparing circuit 206 suppresses the read dataphase signal RDPS by the replica signal from the reception replica208 to thereby output to the DLL 205 a reception phase adjustingsignal relative to DPS output DRAM internal clocks with respect toonly the write data phase signal WDPS.

[0230] Further, the shown DLL 205 delays the data reception DRAMinternal clocks by two clocks to thereby output DRAM internalclocks for outputting the read data phase signal RDPS, data outputfeedback clocks, and data output DRAM internal clocks. Among them,the DPS output DRAM internal clocks are given to the DPS outputdriver 207 and the output phase comparing circuit 209, while thedata output DRAM internal clocks are fed to the data output driver201. Further, the data output feedback clocks are given to anoutput replica 210, and the output replica 210 outputs a replicasignal of the read data phase signal RDPS to the output phasecomparing circuit 209. The DPS output driver 207 sends out the readdata phase signal RDPS to the buffer 105 in response to the DPSoutput DRAM internal clocks.

[0231] While suppressing the timing of the write data phase signalWDPS by the read replica signal given from the output replica 210,the output phase comparing circuit 209 compares phases of the readdata phase signal RDPS and the output of the DLL 205 and outputs tothe DLL 205 an output phase adjusting signal depending on acomparison result. As a result, the read data phase signal RDPS istransmitted from the shown DRAM 110 to the buffer 105.

[0232] As described above, in the shown DRAM 110, when the DRAM 110transmits the read data phase signal RDPS, the DPS output DRAMinternal clocks are outputted so as not to perform phase comparisonand, when receiving the write data phase signal WDPS, the DPSoutput DRAM internal clocks are inputted into the reception phasecomparing circuit 206 to thereby perform an operation to inhibitfeedback of a comparison value to the DLL 205.

[0233] Referring to FIG. 24, description will be given about aconcrete configuration of the buffer 105 that performs datatransmission/reception relative to the DRAM 110 shown in FIG. 23.Like the DRAM 110 shown in FIG. 23, the buffer 105 is provided witha DQ output driver 301 for outputting data to the DRAM 110, and adata receiver 302 for receiving read data from the DRAM 110, andfurther provided with a DLL 305 forming a clock reproduction phaseadjusting and frequency multiplier circuit for data phase signalDPS transmission/reception. Further, in the shown buffer 105, DPSoutput buffer internal clocks are produced by a non-shown clockgenerator, and fed to a DPS output driver 307 and a reception phasecomparing circuit 306. The DPS output driver 307 divides the givenclocks to quarter in frequency to thereby output a write data phasesignal DPS (i.e. WDPS) to the DRAM 110, and the write data phasesignal WDPS is also given to the DLL 305 and the reception phasecomparing circuit 306 within the buffer 105.

[0234] In this state, when the read data phase signal RDPS isreceived from the DRAM 110, the DLL 305 of the buffer 105 producesdata reception buffer internal clocks and data reception feedbackclocks, and outputs them to the data receiver 302 and a receptionreplica 308, respectively. The reception replica 308 produces areplica signal of the read data feedback signal RDPS from the datareception feedback clocks, and outputs it to the reception phasecomparing circuit 306. As a result, the reception phase comparingcircuit 306 ignores the write data phase signal WDPS outputted fromthe DPS output driver 307, and outputs to the DLL 305 a receptionphase adjusting signal with respect to a phase of the read dataphase signal RDPS.

[0235] In the shown buffer 105, for reproducing the clocks from theread data phase signal RDPS from the DRAM 110, the DPS outputbuffer internal clock signal is inputted into the reception phasecomparing circuit 306 to thereby inhibit feedback of a comparisonvalue to the DLL.

[0236] FIG. 25 shows a timing chart upon the start of operation inthe DRAM 110 shown in FIG. 23, and FIG. 26 shows a timing chartduring a normal operation of the DRAM 110. Upon the start ofoperation shown in FIG. 25, a read data phase signal RDPS is notoutputted to the buffer 105 from the DRAM 110. In FIG. 25, like inFIG. 22, DPS output buffer internal clocks of 666 MHz are producedin the buffer 105, and are divided to quarter in frequency at theDPS output driver 307 (FIG. 24) so that a write data phase signalWDPS is outputted synchronously with the clocks (see the secondline in FIG. 25). The write data phase signal WDPS is inputted intothe DRAM 110 with a time delay (see the third line). In the DRAM110, data reception feedback clocks having an advanced phaserelative to the received WDPS are produced at the DLL 205 (see thefourth line) and outputted to the reception replica 208, and areplica signal of the WDPS is outputted from the reception replica208 to the reception phase comparing circuit 206 (see the fifthline).

[0237] Following a reception phase adjusting signal from thereception phase comparing circuit 206 and the received WDPS, theDLL 205 of the DRAM 110 outputs data reception DRAM internal clocksto the data receiver 202 (see the sixth line). Further, the DLL 205of the DRAM 110 outputs to the output replica 210 data outputfeedback clocks having an advanced phase relative to the internalclocks (see the seventh line), and outputs to the DQ output driver201 data output DRAM internal clocks synchronously with the dataoutput feedback clocks (see the ninth line). Further, as shown atthe eighth line in FIG. 25, a data output feedback signal is fed tothe output phase comparing circuit 209 as a replica signal from theoutput replica 210, and phase comparison is performed with thepresence of this replica signal so that DPS output DRAM internalclocks as shown at the tenth line is outputted to the DPS outputdriver 207.

[0238] Now, referring to FIG. 26, the normal operation of the DRAM110 shown in FIG. 23 will be described. In this case, as shown atthe second and third lines in FIG. 26, a write data phase signalWDPS is outputted from the buffer 105, while a read data phasesignal RDPS (see thick lines) is outputted from the DRAM 110. Inthis case, at the buffer 105, DPS output clocks are produced, andthe write data phase signal WDPS synchronous with the DPS outputclocks is transmitted to the DRAM 110, while, at the DRAM 110, datareception feedback clocks, a replica signal of the data receptionfeedback clocks, data reception DRAM internal clocks, data outputfeedback clocks, and data output DRAM internal clocks are produced,which is the same as FIG. 25 (see the fourth to eighth lines).Further, as shown at the ninth line, when the data output DRAMinternal clocks are produced, the DLL 205 produces DPS output DRAMinternal clocks by delaying the internal clocks by two clocks and,according to the DPS output DRAM internal clocks, a read data phasesignal RDPS is produced from the DPS output driver 207 as shown bythick lines at the tenth line, and is received at the buffer 105 asshown at the second line.

[0239] FIG. 27 shows a timing chart in the buffer 105 (FIG. 24)when the foregoing RDPS is received. It is assumed that datatransmitted from the DRAM 110 is matched in phase with edges of theread data phase signal RDPS in this embodiment. In this connection,the buffer 105 shifts a phase of the reception buffer internalclocks by 1/4 relative to a phase of a replica signal from thereception replica 308 which is obtained from the data receptionfeedback clocks.

[0240] In the foregoing examples, there have been shown the systemswherein when the internal clock signals are reproduced from thedata phase signals, the clocks are reproduced directly from thedata phase signals.

[0241] Referring to FIGS. 28 and 29, there are shown modificationsof the DRAM 110 and the buffer 105 respectively shown in FIGS. 23and 24. The DRAM 110 shown in FIG. 28 differs from the DRAM 110shown in FIG. 23 in that clocks CLK are given to a DLL 205 from theexterior, and a data phase signal DPS is not given to the DLL 205.In this connection, the shown DLL 205 not only operates as a clockreproduction phase adjusting circuit, but also operates as afrequency divider for dividing a frequency of clocks. In thisconfiguration, it is seen that, upon clock reproduction, theexternal clock signal CLK is fed to the DLL 205 as a clock source,only a phase of the signal CLK is adjusted at the DLL 205. In thismanner, by giving the external clocks CLK to the DLL 205 andadjusting the phase of the clocks by the DLL 205, it is alsopossible to reproduce data reception DRAM internal clocks and datareception feedback clocks from the received write data phase signalWDPS, and further possible to produce DPS output DRAM internalclocks to thereby transmit a read data phase signal RDPS to thebuffer 105.

[0242] The buffer 105 shown in FIG. 29 also differs from the buffer105 shown in FIG. 24 in that a buffer internal clock signal isgiven to a DLL 305 that operates as a clock phase adjustingcircuit. When the buffer 105 having the configuration shown in FIG.29 is used, the DLL 305 adjusts a phase of clocks according to areception phase adjusting signal from a reception phase comparingcircuit 306 to thereby produce data reception buffer internalclocks and data reception feedback clocks.

[0243] Referring to FIG. 30, description will be given aboutoperations of the buffer 105 and the DRAM 110 shown in FIGS. 28 and29. In this example, an operation in the initial state of the DRAM110 is shown wherein the DRAM 110 does not output the read dataphase signal RDPS. As compared with FIG. 25, the example shown inFIG. 30 differs therefrom in that external clocks of 666 MHz areproduced in the DRAM 110 like in the buffer 105 (see the thirdline). The other operations are the same as those in FIG. 25 exceptthat the operations are performed referring to such externalclocks, and therefore, description thereof is omitted herein.

[0244] Referring to FIGS. 31 to 33, description will be given aboutanother example of a transmission system between the buffer 105 andthe DRAM 110 in the memory system according to the presentinvention. In the foregoing example, the description has been givenabout the case wherein the data phase signals DPS are outputtedbidirectionally from the buffer 105 and the DRAM 110 as the writeand read data phase signals WDPS and RDPS. In FIG. 31, it is seenthat a write data phase signal WDPS and a read data phase signalRDPS are outputted onto different signal lines from the buffer 105and the DRAM 110. Other clocks (CLK), command/address (Cmd/Add),and data DQ are the same as those in FIG. 18. By employing thisconfiguration, it is not necessary to multiplex the two data phasesignals WDPS and RDPS onto the single signal line, so that theconfiguration of the DLL used in each of the buffer 105 and theDRAM 110 can be simplified.

[0245] Referring to FIG. 32, description will be given about anoperation, upon data writing, of the DRAM 110 shown in FIG. 31. Inthis case, a write command WRT and an address (Add) are outputtedto the DRAM 110 from the buffer 105 synchronously with clocks. Inthis event, a write data phase signal WDPS is transmitted to theDRAM 110 from the buffer 105 while being obtained by dividing theclocks CLK to quarter in frequency (see the fourth line in FIG.32). In the DRAM 110, according to internal clocks produced byusing the write data phase signal WDPS as a reference, data DQ iswritten into the DRAM 110 after a lapse of a predetermined latencytime (see the fifth line).

[0246] On the other hand, in the DRAM 110, a read data phase signalRDPS is outputted onto a signal line different from that for thewrite data phase signal WDPS, at timing different from thereception timing of the write data phase signal WDPS.

[0247] As shown in FIG. 33, when a read command (RED) and anaddress (Add) are received at the DRAM 110, the DRAM 110 outputsread data DQ (see the fifth line) to the buffer 105 according tointernal clocks (see the first line) produced based on a read dataphase signal RDPS (see the fourth line). As clear from the figure,the output timing of the read data phase signal RDPS differs fromthe reception timing of the write data phase signal WDPS. In thisexample, the write data phase signal WDPS and the read data phasesignal RDPS are shifted in phase by two clocks therebetween foravoiding output noise such as mutual interference or crosstalktherebetween.

[0248] Now, referring to FIGS. 34 and 35, description will be givenabout concrete examples of the DRAM 110 and the buffer 105 shown inFIG. 31. When comparing the DRAM 110 shown in FIG. 34 and the DRAM110 shown in FIG. 23, the DRAM 110 of FIG. 34 differs from the DRAM110 of FIG. 23 in that the write data phase signal WDPS and theread data phase signal RDPS are inputted thereinto via mutuallydifferent signal lines. In this connection, a read data phasesignal output driver 207' is connected to the read data phasesignal RDPS transmission signal line, but disconnected from a DLL205 of the DRAM 110 and the signal line of the write data phasesignal WDPS, which differs from FIG. 23. The other components arethe same as those in FIG. 23.

[0249] Further, the buffer 105 shown in FIG. 35 differs from thebuffer 105 shown in FIG. 24 in that a write data phase signal WDPStransmission driver 307' is connected to the write data phasesignal transmission signal line, but disconnected from the readdata phase signal RDPS reception signal line and a DLL 305 of thebuffer 105. The other components are the same as those in FIG.24.

[0250] Here, a timing relationship between the DRAM 110 and thebuffer 105 shown in FIGS. 34 and 35 will be schematically describedwith reference to FIG. 36. First, as shown in FIG. 36, the buffer105 produces clocks having a frequency of 666 MHz (see the firstline), and divides the produced clocks to quarter in frequency tothereby output a write data phase signal WDPS onto the write dataphase signal line (see the second line). As shown at the thirdline, the write data phase signal WDPS is received at the DRAM 110with a time delay. The DRAM 110 increases the received write dataphase signal WDPS four times in frequency to thereby produceinternal clocks having a frequency of 666 MHz (see the fourthline), then shifts the produced internal clocks by two clocks anddivides them to quarter in frequency to thereby output a read dataphase signal RDPS as shown at the fifth line onto the read dataphase signal line. The read data phase signal RDPS is received atthe buffer 105 at the timing shown at the sixth line, and thebuffer 105 produces data reception internal clocks from thereceived read data phase signal RDPS as shown at the seventhline.

[0251] Referring also to FIG. 37, further detailed description willbe given about an operation, during a normal time, of the DRAM 110shown in FIG. 34. Since operations upon the start are the same inthe DRAM 110 of FIG. 34 and the DRAM 110 of FIG. 23, descriptionthereof is omitted. The DRAM 110 shown in FIG. 34 is given thewrite data phase signal WDPS from the buffer 105 via the write dataphase signal line (see the third line in FIG. 37), and the writedata phase signal WDPS is received at the DLL 205, the receptionphase comparing circuit 206, and the output phase comparing circuit209 in FIG. 34. As a result, the reception phase comparing circuit206 and the output phase comparing circuit 209 are given write dataphase signals WDPS as shown at the fifth and eighth lines in FIG.37 as input signals, respectively.

[0252] The DLL 205 refers also to a reception phase adjustingsignal and an output phase adjusting signal from the receptionphase comparing circuit 206 and the output phase comparing circuit209 to thereby output data reception feedback clocks shown at thefourth line and data reception DRAM internal clocks shown at thesixth line in FIG. 37 to the reception replica 208 and the datareceiver 202, respectively.

[0253] Further, the DLL 205 feeds data output feedback clocks anddata output DRAM internal clocks shown at the seventh and ninthlines to the output replica 210 and the DQ output driver 201,respectively. Of them, the data output DRAM internal clocks aredivided to quarter in frequency at the DLL 205 and, as shown at thetenth line, fed to the RDPS output driver 207' as RDPS output DRAMinternal clocks. From the output driver 207', a read data phasesignal RDPS shown at the eleventh line is outputted to the buffer105.

[0254] Referring to FIGS. 35 and 38, description will be givenabout an operation of the buffer 105 upon read data reception. Bythe use of WDPS output buffer internal clocks (see the third line),a write data phase signal WDPS is outputted onto the correspondingsignal line (see the second line), and the read data phase signalRDPS is given to the DLL 305 and the reception phase comparingcircuit 306 in the buffer 105 via the read data phase signal line(see the fifth line). The DLL 305 refers to a reception phaseadjusting signal from the reception phase comparing circuit 306 tothereby feed data reception feedback clocks and data receptionbuffer internal clocks shown at the fourth and sixth lines to thereception replica 308 and the data receiver 302. Here, the showndata reception buffer internal clocks are shifted by 1/4 phaserelative to the read data phase signal RDPS.

[0255] Referring to FIGS. 39 and 40, description will be givenabout other examples of a DRAM 110 and a buffer 105 that canrealize the transmission system shown in FIG. 31. The DRAM 110shown in FIG. 39 differs from the DRAM 110 shown in FIG. 34 in thatclocks CLK are given from the exterior like in FIG. 28. On theother hand, the buffer 105 shown in FIG. 40 differs from the buffer105 shown in FIG. 35 in that a buffer internal clock signal isgiven to a DLL 305 in the buffer 105. In FIG. 39, the externalclocks are given to a DLL 205 in the DRAM 110, while a write dataphase signal WDPS is fed to a reception phase comparing circuit 206and an output phase comparing circuit 209. With this configuration,an operation like that in FIG. 34 can also be realized.

[0256] In the buffer 105 shown in FIG. 40, a read data phase signalRDPS from the DRAM 110 is given to a reception phase comparingcircuit 306, and the DLL 305 produces data reception feedbackclocks and data reception buffer internal clocks according to areception phase adjusting signal from the reception phase comparingcircuit 306 and the buffer internal clock signal. With thisconfiguration, an operation like that in FIG. 35 is madepossible.

[0257] In the foregoing transmission systems, the description hasbeen given about the data transmission between the buffer and theDRAM that are mounted on the memory module. However, the presentinvention is not at all limited thereto. For example, the presentinvention is also applicable to a memory circuit other than a DRAM,e.g. a ROM. Further, the present invention can achieve high-speeddata transmission even if it is applied to the system that requiresbidirectional data transmission or that requires a strobesignal.

[0258] In the foregoing memory systems, the buffer and theplurality of DRAMs are mounted on each memory module, andreception/transmission of data signals relative to the DRAMs on thememory module and transmission of clocks and address/commandsignals relative to the DRAMs are all carried out via the buffer oneach memory module. Further, in the foregoing, the description hasbeen mainly given about one-to-one data reception/transmissionbetween the buffer and each of the DRAMs on each memory module.

[0259] However, for actually operating the foregoing memory moduleat high speed, it is further necessary to process timing skews thatare generated between data signals, and clocks and command/addresssignals depending on positions of the DRAMs on the memory module,and moreover, to perform matching of clock timings in the bufferrelative to data that are transmitted from the respective DRAMs andarrive at the buffer at different timings.

[0260] Here, referring to FIG. 41, the foregoing point will bedescribed more specifically. A buffer 105 and a plurality of DRAMs110 are mounted on a shown memory module 103. The package size ofeach DRAM 110 mounted on the memory module 103 normally has a widthof about 14 mm, and this size is considered to be maintained evenif the generation is advanced. When the DRAMs 110 each having sucha size are mounted as shown in the figure, for example, when thefive DRAMs 110 are mounted at regular intervals of 9 mm, a wiringlength of each of a clock line, a command/address ling, and a DQsignal line between the far-end DRAM 110 (denoted by 110F) and thebuffer 105 is 65 mm, while a wiring length thereof between thenear-end DRAM 110 (denoted by 110N) and the buffer 105 is 9 mm.

[0261] When the memory module 103 thus dimensioned is operated at ahigh frequency of 800 MHz, a timing skew of a level that can not beignored relative to an operation period (1250 ps) of thehigh-frequency operation (800 MHz) is generated at the far-end DRAM110F due to a difference in signal propagation time between theclocks and the command/address signal, and the DQ signal.

[0262] More specifically, since the clocks and the command/addresssignal are inputted into the respective DRAMs 110 from the buffer105 via the common wiring, an input capacitance of about 1.5pF.times.2.times.5 is distributed on the wiring relative to theclocks and the command/address signal. Therefore, a signal unitpropagation time (tPD) of the clocks and the command/address signalbecomes about 14 ps/mm. On the other hand, the DQ signal istransmitted/received between the buffer and the respective DRAMs110 via one-to-one or one-to-two wiring, and therefore, an inputcapacitance of about 2.5 pF.times.2 is distributed on the wiringrelative to the DQ signal. Therefore, a signal unit propagationtime tPD of the DQ signal becomes about 8 ps/mm, and thus it isunderstood that the signal unit propagation time of the DQ signalis shorter than the signal unit propagation time of the clocks andthe command/address signal.

[0263] Based on such a difference in signal propagation timebetween the clocks and the command/address signal, and the DQsignal, the timing skew of the level that can not be ignoredrelative to the operation period (1250 ps) of the high-frequencyoperation (800 MHz) is generated at the far-end DRAM 110F. In theshown memory system, a signal propagation time of the clocks andthe command/address signal upon writing is 910 (=14.times.65) ps,while a signal propagation time of the DQ signal is 520(=8.times.65) ps. As a result, a timing skew of 390 ps is generatedbetween the clocks and the command/address signal, and the DQsignal at the far-end DRAM 110F.

[0264] When a write command (WRT) is given to the far-end DRAM 110Fin the state where such a timing skew is generated, the writecommand is inputted into the DRAM at a phase of a buffer clocksignal from the buffer 105.

[0265] On the other hand, a data write operation in each DRAM 110is implemented synchronously with the buffer clock signal after thereception of the write command. This means that data received atleading edges of the data reception DRAM internal clocks should bematched with the phase timing of the buffer clock signal during onecycle.

[0266] For example, data received at leading edges of the datareception DRAM internal clocks are matched with the clock signalphase timing at trailing edges of the buffer clock signal, whiledata received at trailing edges are matched with the clock signalphase timing at leading edges of the buffer clock signal. As aresult, internal data are alternately produced. When shiftingmatching of such data from one timing to another timing, a setuptime and a hold time are required.

[0267] In the system shown in FIG. 41, a setup time and a hold timeat the near-end DRAM 110N for shifting matching of data received atthe timing of the data reception DRAM internal clocks to the bufferclock timing are 679 ps and 571 ps, respectively, while a setuptime and a hold time at the far-end DRAM 110F are 1015 ps and 235ps, respectively.

[0268] As clear from this, since a timing skew between the clocksignal and the DQ signal is 54 ps, i.e. small, at the near-endDRAM, uniform margins are obtained for the setup time and the holdtime, while, the hold time becomes 235 ps (0.19 clock period), i.e.short, at the far-end DRAM 110F due to the skew of 390 ps, so thata sufficient time margin can not be obtained.

[0269] Further, DQ signals transmitted from the respective DRAMs inresponse to a read (READ or RED) command arrive at the buffer 105at different arrival times due to a difference between apropagation time of the clock signal (equal to a propagation timeof the command) and a propagation time of the DQ signal. Forexample, a propagation time of the clock signal (command) to thenear-end DRAM 110N is 126 ps and a propagation time of the DQsignal to the buffer 105 from the near-end DRAM 110N is 72 ps,while a propagation time of the clock signal (command) to thefar-end DRAM 110F is 910 ps and a propagation time of the DQ signalto the buffer 105 from the far-end DRAM 110F is 520 ps.

[0270] Assuming that a latency from a read command to data outputis equal among the respective DRAMs, e.g. eight clocks here, thetotal signal two-way propagation time at the near-end DRAM 110N is198 ps, while the total signal two-way propagation time at thefar-end DRAM 110F is 1430 ps, i.e. a difference therebetween is1230 ps.

[0271] Therefore, at the buffer 105, it is necessary to match thedata of different arrival times with the timing of the clock signalagain, and transfer them to the memory controller. Further, asclear from the foregoing, data from the near-end DRAM 110N and datafrom the far-end DRAM 110F arrive spanning different clock cycleswithin the buffer 105. Therefore, it is necessary to judge at thebuffer 105 per data from each DRAM 110 as to which cycle it shouldbe matched with.

[0272] Hereinbelow, referring to the drawings, description will begiven about examples of the present invention that take theforegoing skew into account.

[0273] In the following examples, it is assumed that a clock signalfed to each DRAM (herein, called "buffer clock signal") is producedby dividing clocks fed to the buffer 105 (herein, called "globalclocks") to half in frequency for the purpose of processing theforegoing skew, and a DPS signal is transmitted at a frequencyequal to that of the produced buffer clock signal. Therefore, thecommand/address signal is transmitted/received synchronously withleading and trailing edges of the clock signal. Further, a datasignal is received/transmitted synchronously with the DPS signal ata transfer rate that is four times a frequency of the clocksignal.

[0274] Referring to FIG. 42, there is shown a configuration of aDRAM that is used in a memory system according to a first exampleof the present invention, wherein write/read data phase signals(WDPS/RDPS) are inputted/outputted via mutually differentwirings.

[0275] The DRAM 110 shown in FIG. 42 is provided with acommand/address reception clock generating circuit (DLL) 500 and adomain crossing circuit 501, which differs from the DRAMs 110 shownin other figures. The shown clock generating circuit (DLL) 500 anddomain crossing circuit 501 operate in response to reception of abuffer clock signal and a command/address signal each having afrequency of 400 MHz from the buffer, respectively.

[0276] In the shown example, the command/address signal is receivedinto the DRAM 110 at the timing of the buffer clock signal(hereinafter, it may also be referred to simply as "clock signal"),and delivered to data phase clocks within the DRAM 110 producedbased on the data phase signal (WDPS). Through this, thecommand/address signal becomes an internal command produced basedon the data phase (WDPS), and thereafter, an internal read/writeoperation of the DRAM 110 is carried out according to this internalcommand. This means that the internal read/write operation of theDRAM 110 is implemented synchronously with the data phase of theWDPS.

[0277] Here, for allowing the phase of the clocks in the DRAM 110to allocate margins to a setup time and a hold time relative to thephase of the delivery-destination WDPS, the WDPS signal is delayedby one clock (represented by 1tCK) of the global clocks, i.e. by180 degrees of the divider clocks, in the buffer 105.

[0278] Referring to FIG. 43, there is shown a concreteconfiguration of the domain crossing circuit 501 provided in theDRAM 110. The shown domain crossing circuit 501 is a circuit fordomain-crossing the command/address signal from the phase of thebuffer clock signal to the WDPS phase, and comprises a first latchcircuit 511 and a second latch circuit 512. Specifically, the firstlatch circuit 511 comprises two receivers for receiving a commandsignal according to 0-degree phase clocks and 180-degree phaseclocks and latching it, while the second latch circuit 512comprises two flip-flop circuits for holding the command signalfrom the first latch circuit 511 according to 0-degree data phaseclocks and 180-degree data phase clocks.

[0279] Here, the 0-degree and 180-degree phase clocks are producedat the command/address reception clock generating circuit 500 shownin FIG. 42, and represent 0-degree and 180-degree phases of thereceived buffer clock signals, respectively. On the other hand, the0-degree and 180-degree data phase clocks represent 0-degree and180-degree phases of the write data phase signal (WDPS),respectively.

[0280] As shown in FIG. 42, the 0-degree and 180-degree data phaseclocks are produced at a clock reproduction and phase adjustingcircuit (DLL) 205 that operates in response to the WDPS.

[0281] As clear from this, it is understood that the shown domaincrossing circuit 501 shifts synchronization of the command signal(or the address signal) with the 0-degree or 180-degree phase ofthe buffer clock signal to synchronization thereof with the0-degree or 180-degree phase of the data phase signal (WDPS), andoutputs it as a DRAM internal command/address signal.

[0282] Referring to FIG. 44, there is shown a concreteconfiguration of the buffer 105 forming the first example of thepresent invention cooperatively with the DRAM 110 shown in FIG. 42,wherein the buffer 105 implements transmission/reception of thedata signal DQ relative to the DRAM 110 of FIG. 42. The shownbuffer 105 has a clock dividing/phase comparing adjusting circuit601 that operates in response to reception of global clocks givenfrom a memory controller (not shown). The clock dividing/phasecomparing adjusting circuit 601 outputs buffer clocks obtained bydividing the global clocks to half in frequency, to the DRAM 110 asa clock signal, while outputs WDPS for DRAMs. In the figure, thereis shown only a portion of outputting the WDPS for the far-end DRAM110F.

[0283] Further, the shown clock dividing/phase comparing adjustingcircuit 601 internally outputs data output buffer internal clocksand WDPS buffer internal phase clocks to a DQ output driver 301 anda domain crossing circuit 602, respectively. Here, the WDPS bufferinternal phase clocks represent 0-degree, 90-degree, 180-degree and270-degree phases of the WDPS for the far-end DRAM 110F.

[0284] On the other hand, a clock reproducing/phase adjustingcircuit 305, which operates in response to reception of an RDPSbeing a data phase signal from the far-end DRAM 110F, produces datareception buffer internal phase clocks representing 0-degree,90-degree, 180-degree and 270-degree phases of the RDPS, and feedsthem to the domain crossing circuit 602.

[0285] The domain crossing circuit 602 in the buffer 105 comprisesa first-stage data latch circuit 611 and a second-stage data latchcircuit 612. Specifically, the domain crossing circuit 602 is acircuit for domain-crossing from the RDPS phase to the WDPS phaseand, as shown in FIG. 45, comprises the first-stage data latchcircuit 611 for receiving a data signal DQ read from the DRAM 110according to buffer internal phase clocks produced synchronouslywith 0-degree, 90-degree, 180-degree and 270-degree phases of theRDPS, and latching it, and the second-stage data latch circuit 612for latching an output of the first-stage data latch circuit 611.The second-stage data latch circuit 612 comprises flip-flopcircuits respectively latching according to WDPS buffer internalphase clocks (270, 0, 90 and 180 degrees) produced at the clockdividing/phase comparing adjusting circuit 601 shown in FIG. 44,and latches the output from the first-stage data latch circuit 611at the phases of the WDPS buffer internal phase clocks, thenoutputs it as a buffer internal data signal.

[0286] Referring to FIG. 46, description will be given about anoperation of the shown example upon writing. Here, description willbe given about an operation between the buffer 105 and the near-endDRAM 110N upon writing. Herein, it is assumed that, for matchingthe command/address signal with the global clocks in each DRAM 110,i.e. for shifting the command/address signal from the phase domainof the buffer clocks to the phase domain of the WDPS, the buffer105 outputs the WDPS to the near-end DRAM 110N by delaying the WDPSby one system clock time phase (1250 ps), and a write latency (WL)is six system clocks.

[0287] As shown in the figure, when global clocks of 800 MHz (seethe first line) are received, the clock dividing/phase comparingadjusting circuit 601 of the buffer 105 outputs buffer clocks of400 MHz (see the second line). Synchronously with the bufferclocks, a write command (WRT) is outputted to the near-end DRAM110N. On the other hand, a write phase signal (WDPS) of 400 MHz isoutputted to the near-end DRAM 110N with a delay of a phasecorresponding to one global clock (1250 ps), i.e. with a delay of1/2 phase of the buffer clock signal. After the foregoing WL, awrite data signal (DQ) is outputted to the near-end DRAM 110Nsynchronously with the WDPS.

[0288] On the other hand, at the near-end DRAM 110N, as describedbefore, the buffer clocks and the write command (WRT) arrive in apropagation time after 126 ps, while the WDPS arrives in a 54ps-shorter propagation time.

[0289] As shown in FIG. 42, at the near-end DRAM 110N, thecommand/address reception clock generating circuit 500 generates0-degree and 180-degree phase clocks representing 0 degrees and 180degrees of the received buffer clocks. Further, the clockreproducing/phase adjusting circuit 205 of the near-end DRAM 110Nreceiving the WDPS generates 0-degree and 180-degree phase dataphase clocks representing 0-degree and 180-degree phases of theWDPS.

[0290] In the shown example, the command/address signal received atthe DRAM synchronously with the clock signal is subjected to domaincrossing from 0-degree phase clocks (phase of buffer clocks) to0-degree phase data phase clocks (0-degree phase of WDPS) and, as aresult, an internal write command (WRT) is produced synchronouslywith the 0-degree phase data phase clocks. This means that thedomain crossing from the buffer clock phase to the WDPS phase hasbeen implemented, and writing of the data signal (DQ) is carriedout after 6 WL in response to the internally produced write command(WRT).

[0291] A setup time and a hold time of the thus configured near-endDRAM 110N for shifting the command/address signal from the clockphase to the data phase are 1196 ps and 1304 ps, respectively, andtherefore, it is seen that a sufficient time margin can beensured.

[0292] The near-end DRAM 110N produces an RDPS in phase with thereceived WDPS and outputs it to the buffer 105, which arrives atthe buffer 105 after a propagation time of 144 ps.

[0293] Referring to FIG. 47, there is shown an operation, uponwriting, between the buffer 105 and the far-end DRAM 110F in thememory system according to the foregoing example. As shown in thefigure, a write command (WRT) is outputted synchronously withbuffer clocks of 400 MHz, while a WDPS is outputted with a delay of1/2 phase of a 1250 ps delayed buffer clock signal relative to thebuffer clocks. The write command (WRT) and the buffer clocks, andthe WDPS reach the far-end DRAM 110F after a lapse of differentdelay times. They are received at the far-end DRAM 110F in thestate where the foregoing skew of 390 ps is generated between thebuffer clocks and the WDPS. At the far-end DRAM 110F, the receivedwrite command WRT is caused to match with the timing of thereceived WDPS to thereby produce a DRAM internal command (WRT)synchronously with the received WDPS, and a data signal (DQ) iswritten after 6 WL from the DRAM internal command.

[0294] As shown in the figure, a hold time and a setup time of thethus configured far-end DRAM 110F for shifting the command/addresssignal from the clock phase to the data phase can be 1640 ps and860 ps, respectively. Accordingly, it is seen that a sufficienttiming margin can be ensured.

[0295] Further, as shown in the figure, the far-end DRAM 110Fhaving received the WDPS outputs an RDPS to the buffer 105synchronously with the WDPS, wherein the RDPS has the same phase asthe WDPS. After a lapse of 1040 ps subsequently to the productionof the WDPS, the buffer 105 receives the RDPS having thecorresponding phase from the far-end DRAM 110F. In this example,the RDPS has the same phase as the WDPS. Accordingly, 0-degreephase of the RDPS corresponds to 0-degree phase of the WDPS,90-degree phase of the RDPS corresponds to 90-degree phase of theWDPS, and likewise, 180-degree and 270-degree phases of the RDPScorrespond to 180-degree and 270-degree phases of the WDPS,respectively.

[0296] Now, referring to FIG. 48, description will be given about aread operation in the memory system according to the foregoingexample, wherein the buffer 105 outputs a read command (RED) to thefar-end DRAM 110F synchronously with the buffer clocks. Asdescribed above, when a time of 1040 ps has elapsed after thetransmission of the WDPS, the RDPS having the corresponding phasearrives at the buffer 105 from the far-end DRAM 110F.

[0297] On the other hand, on the side of the far-end DRAM 110F,synchronously with the received WDPS, the RDPS having the samephase is outputted to the buffer 105. The buffer 105 outputs theread command (RED) to the far-end DRAM 110F synchronously withbuffer clocks. The far-end DRAM 110F receives the read command atthe timing of the buffer clock signal and delivers it to the dataphase clocks produced based on the WDPS. As a result, the readcommand signal becomes an internal command produced based on thedata phase (WDPS), and thereafter, an internal read operation ofthe DRAM 110F is implemented by this internal read command. After alapse of eight global clocks from the received RED, a data signal(DQ) is read out. The read-out data signal is outputted to thebuffer 105 from the far-end DRAM 110F synchronously with the RDPSand, after 520 ps, received at the buffer 105.

[0298] In this configuration, the timing margin for domain crossingfrom the RDPS phase to the WDPS phase in the buffer 105 is 835 ps,and therefore, it is understood that the sufficient timing margincan be obtained.

[0299] Further, referring to FIG. 49 and FIG. 44, description willbe given about an operation, upon reading, in the buffer 105 in theforegoing example. Here, it is assumed that a data signal (DQ) isread from the far-end DRAM 110F. At the buffer 105, the read datasignal (DQ) is received synchronously with the received RDPS. Thebuffer 105 shown in FIG. 44 produces, from the RDPS, four-phasedata reception buffer internal clocks (0, 90, 180 and 270 degrees)representing phases of the RDPS, and feeds them to the first-stagedata latch circuit 611 of the domain crossing circuit 602.Therefore, the data signal (DQ) from the far-end DRAM 110F isstored into the first-stage data latch circuit 611 synchronouslywith those four-phase data reception buffer internal clocks, thenfed to the second-stage data latch circuit 612.

[0300] Four-phase buffer internal phase clocks obtained from theWDPS (global clocks) produced at the buffer 105 are given to thesecond-stage data latch circuit 612 from the clock dividing/phasecomparing adjusting circuit 601, and an output of the first-stagedata buffer 611 is stored into the second-stage data latch circuit612 according to the four-phase buffer internal phase clocks. As aresult, the data signal (DQ) read from the far-end DRAM 110F iscaused to match with the internal clocks produced in the buffer105, so as to be outputted to the memory controller from the buffer105.

[0301] Now, referring to FIG. 50, description will be given aboutan operation of the buffer 105 when processing data signals (DQ)from the near-end and far-end DRAMs 110N and 110F upon reading. Itis assumed that read commands (RED) and WDPS delayed by 1/2 phaserelative to buffer clocks are outputted to the near-end and far-endDRAMs 110N and 110F from the buffer 105 synchronously with thebuffer clocks. In this case, as shown in the figure, an RDPS signalhaving the same phase as a corresponding phase of a WDPS signal isinputted into the buffer 105 at timing delayed by 144 ps from thenear-end DRAM 110N, while it is inputted into the buffer 105 attiming delayed by 1040 ps from the far-end DRAM 110F. Here,assuming that the buffer 105 is set to start a data take-inoperation at a time instant when (8+2.5) global clock time elapsesafter production of the read command (RED), hold times for shiftingthe timing of the data signals (DQ) that are read out synchronouslywith the RDPS of the near-end and far-end DRAMs, from the RDPSphase to the WDPS phase, i.e. the clock phase, in the buffer 105are 770 ps and 1665 ps, respectively, and setup times therefor are1731 ps and 835 ps, respectively, and therefore, it is understoodthat sufficient time margins are ensured.

[0302] The foregoing operation will be described in a moregeneralized manner. A buffer clock signal obtained by n-dividing(dividing by n) a system clock (global clock) signal in frequency,and a data phase signal (WDPS) having a frequency equal to that ofthe buffer clock signal are fed to the DRAMs from the buffer 105.On the other hand, command/address signals are transmitted from thebuffer 105 while being matched with the buffer clock signal. Whenthe command/address signals transferred in a period are m times atmaximum, each command/address signal is received by one of internalclock signals produced per 1/m phase from the timing of the bufferclock signal at the DRAM.

[0303] On the other hand, in each DRAM 110, the command/addresssignal is delivered to previously associated one of internal dataphase clocks that are internally produced per 1/m phase, likewise,from the timing of the data phase signal (WDPS) transmitted fromthe buffer 105, so that an internal command/address signal isproduced.

[0304] Data signals written into the respective DRAMs 110 aretransmitted to the DRAMs 110 from the buffer 105 while beingmatched with the timing of the data phase signal (WDPS). When thedata signals transferred in a period are k times at maximum, thedata signal is received at each DRAM 110 and stored therein by oneof internal clock signals that are produced at the DRAM 110 per 1/kphase from the timing of the data phase signal (WDPS) transmittedfrom the buffer 105.

[0305] On the other hand, the data signal read from each DRAM 110is transmitted from the DRAM 110 while being matched with thetiming of the data phase signal (RDPS), and received at the buffer105 by one of internal clock signals produced per 1/k phase fromthe timing of the data phase signal (RDPS) transmitted from theDRAM 110. This RDPS is delivered to previously associated one ofinternal clocks produced per 1/k phase from the timing of the dataphase signal (WDPS) that is originally produced in the buffer 105,so that an internal read data signal is produced.

[0306] In this case, the command/address signal is transmitted tothe buffer 105 synchronously with leading and trailing edges of thebuffer clock signal, and taken into the DRAM synchronously withleading and trailing edges of the buffer clock signal.

[0307] Referring to FIG. 51, there is shown a DRAM 110 that is usedin a memory system according to a second example of the presentinvention. The DRAM 110 according to this example is configured totake in a data signal using phase clocks produced from a WDPS anddeliver it to phase clocks produced from a buffer clock signal.Therefore, the shown DRAM 110 comprises a clock reproducing/phaseadjusting circuit 521 that operates in response to reception of theWDPS, and the clock reproducing/phase adjusting circuit 521 isconnected to a reception replica 523 and a reception phasecomparing circuit 525. Under the control of a reception phaseadjusting signal from the reception phase comparing circuit 525,the shown clock reproducing/phase adjusting circuit 521 producesfour-phase data reception DRAM internal phase clocks (0, 90, 180and 270 degrees) from the WDPS and feeds them to a first-stage datalatch circuit 527 of a domain crossing circuit 501.

[0308] On the other hand, the buffer clock signal is given to aclock reproducing/phase adjusting circuit (DLL) 205 which producesfour-phase phase clocks therefrom and feeds them to a second-stagedata latch circuit 529 of the domain crossing circuit 501.

[0309] Referring also FIG. 52, the first-stage data latch circuit527 of the domain crossing circuit 501 is given a data signal (DQ)from the buffer 105, and further given from the clockreproducing/phase adjusting circuit 521 four-phase data receptionDRAM internal phase clocks produced from the WDPS. Therefore, thefirst-stage data latch circuit 527 composed of fourreceivers/latches receives the data signal (DQ) at timing of thefour-phase data reception DRAM internal clocks and latches it, andfeeds outputs thereof to the second-stage data latch circuit 529composed of four flip-flop circuits, respectively.

[0310] Four-phase DRAM internal phase clocks are respectively givento the four flip-flop circuits of the second-stage data latchcircuit 529, and the outputs from the first-stage data latchcircuit 527 are stored according to the four-phase DRAM internalphase clocks and outputted as a DRAM internal data signal.

[0311] Further, the clock reproducing/phase adjusting circuit 205produces two-phase phase clocks of 0 and 180 degrees from thebuffer clock signal and feeds them to a command/address receiver531. The command/address receiver 531 takes in a command/addresssignal according to the two-phase phase clocks and outputs it as aninternal command/address signal. Accordingly, the internalcommand/address signal is produced at the buffer clock phase, andan internal read/write operation of the DRAM is implementedsynchronously with the buffer clock phase.

[0312] Referring to FIG. 53, there is shown a specific example ofthe buffer 105 that is used while being connected to the foregoingDRAM 110. A clock dividing/phase comparing adjusting circuit 601included in the shown buffer 105 feeds buffer internal four-phasephase clocks to a domain crossing circuit 602, and further outputsdata output buffer internal four-phase clocks to a DQ output driver301, which differs from the buffer 105 shown in FIG. 44. Further,the shown domain crossing circuit 602 is given data receptionbuffer internal four-phase clocks produced based on the RDPS from aclock reproducing/phase adjusting circuit 305.

[0313] Referring also to FIG. 54, a first-stage data latch circuit611 of the domain crossing circuit 602 shown in FIG. 53 comprisesfour receivers for receiving a data signal (DQ) according to thefour-phase data reception buffer internal phase clocks and latchingit, and outputs of the respective receivers are fed to fourflip-flop circuits forming a second-stage data latch circuit 612,respectively. These flip-flop circuits latch the outputs of thefirst-stage data latch circuit according to the four-phase bufferinternal phase clocks. As shown in the figure, the outputs receivedand latched in the first-stage data latch circuit 611 according tothe 0, 90, 180 and 270-degree data reception buffer phase clocks,i.e. the clocks representing the RDPS, are latched in thesecond-stage data latch circuit 612 according to the 270, 0, 90 and180-degree internal phase clocks, respectively, and therefore, itis understood that the data signal is latched by the differentphase clocks. In other words, in the shown example, it is seen thatshifting to a 90-degree advanced phase is performed in the phase ofthe buffer clock signal.

[0314] Referring to FIG. 55, description will be given about awrite operation between the buffer 105 and the near-end DRAM 110N.The buffer 105 outputs a WDPS to the near-end DRAM 110N. Forensuring a time margin for shifting a data signal (DQ) from WDPSphase domain to clock phase domain in the DRAM 110, the WDPS has aphase that is advanced by 90degrees (1/2 clock in terms of globalclocks; 625 ps) relative to the buffer clock signal.

[0315] In the figure, a write command (WRT) is outputted to thenear-end DRAM 110N from the buffer 105 synchronously with thebuffer clocks. On the other hand, after a write latencycorresponding to six clocks of the global clocks, the data signal(DQ) is outputted from the buffer 105 synchronously with theWDPS.

[0316] The buffer 105 outputs the buffer clocks and the writecommand (WRT) synchronous with the buffer clocks, and furtheroutputs the WDPS while matching it with the buffer clocks.

[0317] In this event, the write command (WRT) and the WDPS (i.e.DQ) are received at the near-end DRAM 110N while having apropagation delay difference of 54 ps therebetween.

[0318] After 6 WL (write latency) from the received write command,when the data signal (DQ) is outputted from the buffer 105synchronously with the WDPS, it is inputted into the DRAM 110Naccording to the data phase clocks produced from the WDPS, anddelivered to the phase clocks produced from the buffer clocksignal. Herein, a hold time and a setup time for domain crossingfrom the data phase to the clock phase are 1821 ps and 679 ps,respectively. The shown near-end DRAM 110N outputs the RDPS to thebuffer 105 at the timing of the received buffer clocks. After 72ps, i.e. after 198 ps from a corresponding phase of the globalclocks, the RDPS is inputted into the buffer 105.

[0319] Referring to FIG. 56, there is shown a write operationrelative to the far-end DRAM 110F. In this case, assuming thatthere exists a skew propagation delay time difference of 390 psbetween a write command (WRT) and a data signal (DQ) which arereceived at the far-end DRAM 110F, there also exists a like skewbetween buffer clocks and a WDPS. Taking this into account, thephase of the WDPS is advanced by 90 degrees, and domain crossingfrom the WDPS phase to the buffer clock phase is carried out. As aresult, even in the far-end DRAM 110F, as shown in the figure, ahold time of 1485 ps and a setup time of 1015 ps are ensured fordomain crossing from the data phase to the clock phase, so that asufficient timing margin is obtained.

[0320] Further, upon reading, as shown in FIG. 57, the DRAM 110transmits an RDPS to the buffer 105 so as to be in phase with thebuffer clock phase, and a data signal (DQ) is transmitted to thebuffer 105 while being matched with the RDPS. The buffer 105 takesin the data signal according to a phase clock signal produced fromthe RDPS. In this manner, by delivering the data signal to thephase clock signal produced based on the clock signal within thebuffer 105, it is possible to match it with the clock phase in thebuffer 105.

[0321] In the buffer 105, for allowing the phase of the RDPS in thebuffer 105 to allocate margins to a setup time and a hold timerelative to the phase of the delivery-destination clocks, thedelivery is carried out such that 0 degrees to the RDPS correspondto 270 degrees of the clock signal.

[0322] Through this operation, as shown in FIG. 58, when the readdata from the near-end and far-end DRAMs are received at the buffer105, a sufficient setup time and hold time can be ensured. In theshown example, a hold time of 823 ps and a setup time of 1677 pscan be ensured in the near-end DRAM 110N, while a hold time of 2055ps and a setup time of 445 ps can be ensured in the far-end DRAM110F. In the shown example, in the data signal reading operation,the total latency is equal to the sum of a read-out time and 1.5clocks in the DRAM.

[0323] As clear from the foregoing, the command/address receptionclock generating circuits 500 and 521, the domain crossing circuits501, and the clock reproducing/phase adjusting circuits 205 in theDRAMs 110 shown in FIGS. 42 and 51 operate as DRAM side circuitsfor absorbing a skew between the data signal and thecommand/address signal, while the clock dividing/phase comparingadjusting circuits 601, the domain crossing circuits 602, and theclock reproducing/phase adjusting circuits 305 in the buffer 105shown in FIGS. 44 and 52 operate as buffer side circuits forabsorbing the skew.

[0324] In the foregoing two examples, the clock signal and the dataphase signal (W/RDPS) fed to each DRAM are produced in the buffer105 by 2-dividing (dividing to half or dividing by 2) the systemclock signal (i.e. global clocks) in frequency. Further, in eachDRAM and the buffer 105, the clock phase signal and the data phasesignal are produced per 1/2 phase in case of the command/addresssignal and per 1/4 phase in case of the data signal. Further, theclock phase signal and the data phase signal internally producedand having different phases are associated with each other tothereby shift the timing of the received signal between the clocks.In this case, since the period of each of the associated signal istwice that of the system clock signal, margins to the setup timeand the hold time can be ensured relative to thedelivery-destination phase signal as described above.

[0325] In this case, the margins to the setup time and the holdtime are ideally such that edges of the phase signal taking in thesignal to be delivered are located just at the middle positionsbetween edges of the delivery-destination phase signal. However, incase of signal transmission from the buffer to the DRAM, anadjustment may be performed to retard or advance the phase of theWDPS in the buffer relative to the clock signal, thereby to moreapproximate it.

[0326] Further, when matching the DQ signals from the DRAMs in thebuffer, a delivering-side phase signal may be selected such thatedges of the RDPS from the far-end and near-end DRAMs approximatethe middle positions of the WDPS or the clock signal serving as thedelivery-destination phase signal. In the foregoing examples, it isclear that the 270-degree phase signal of the WDPS or the clocksignal is set to correspond to the 0-degree phase signal of theRDPS, thereby to achieve matching of the timing of the DQ signalsfrom the DRAMs.

[0327] Further, a flight time that is not synchronous with clockson the module until the DQ signal is transferred to the buffer fromthe DRAM becomes a time for the data signal to go and returnbetween the buffer and the DRAM in case of the first example, whileit becomes the sum of a time for the read command to be transmittedfrom the buffer to the DRAM and a time for the data signal to betransmitted from the DRAM to the buffer in case of the secondexample. It becomes 1040 ps at maximum (in case of the far-endDRAM) in the first example, while it becomes 1430 ps at maximum inthe second example. By 2-dividing the system clock signal infrequency, it becomes possible to perform the processing (matchingwith the original clock phase on the buffer) in one cycle (2500ps).

[0328] Referring to FIG. 59, description will be given about amemory system according to a third example of the presentinvention. In this example, a DPS (Data Phase Signal) is used and,while suppressing the increase of the number of wirings,transmission/reception of a DPS of a differential signal is madepossible. This example differs from the other examples in that anRDPS transmitted from each DRAM and a WDPS transmitted from abuffer 105 are transmitted/received via a common signal line, and acontrol signal (indicate) is transmitted to the DRAMs 110 from thebuffer 105. This control signal (indicate) is a signal forswitching, on the side of the DRAM 110, between a time period forreceiving a data phase signal (WDPS) from the buffer 105 and a timeperiod for transmitting a data phase signal (RDPS) to the buffer105. On the other hand, the buffer 105 switchesreception/transmission of a data phase signal (DPS) in the buffer105 according to a control signal (indicate) of itself.

[0329] As shown in FIG. 59, since the control signal can be sharedamong the DRAMs 110 on the memory module, wiring for the controlsignal (indicate) is increased only by one.

[0330] In the memory system (i.e. memory module 103) according tothe foregoing third preferred embodiment, it is necessary toconfigure the driver circuit in open-drain mode when the signalline is shared with the RDPS and WDPS. However, in this example, itmay also be a CMOS push-pull driver, or a differential signal maybe used, so that the timing accuracy can be improved.

[0331] Referring to FIG. 60, there is shown a configuration of theDRAM 110 that is used in this example, while FIG. 61 shows aconfiguration of the buffer 105 likewise used in this example. Asclear from FIG. 61, the buffer 105 is provided with a DPS controlsignal producing circuit 701, and a control signal (indicate) istransmitted to the DRAMs 110 from the DPS control signal producingcircuit 701, while an internal control signal is outputted to aclock dividing/phase comparing adjusting circuit 601, a clockreproducing/phase adjusting circuit 305, and a reception phasecomparing circuit 306 from the DPS control signal producing circuit701.

[0332] On the other hand, the DRAM 110 shown in FIG. 60 is providedwith a DPS control circuit 541 that, in response to reception ofthe control signal (indicate), switches a mode of a DPS driver 207,and changes the state of a clock reproducing/phase adjustingcircuit 521 and a reception phase comparing circuit 525. Inasmuchas the other components have already been explained, no detailsthereof are given here.

[0333] Referring to FIG. 62, there is shown timing for switchingbetween a time period for transmitting the data phase signal fromthe buffer 105 according to the control signal (indicate)transmitted from the buffer 105, and a time period for transmittingthe data phase signal from the DRAM according to the controlsignal. In the shown example, both time periods are switchedalternately.

[0334] FIG. 63 shows a case wherein a switching time period of theindicate is set long during initialization for allowing the DLLs tolock on, while the switching time period is set shorter during anormal operation for fine adjustment as compared with that duringthe initialization. In this manner, the buffer 105 can set theswitching time period to be long during the initialization tothereby allow the DLLs to lock on, while it can set the switchingtime period to be shorter during the normal operation as comparedwith that during the initialization to thereby deal withfluctuation caused by operation noise. In this configuration,although a phase locking time at the DRAM becomes long during theinitialization that requires fine adjustment, inasmuch as variationin phase due to operation noise is small, no problem is raised.

[0335] In the foregoing examples, the setup time and the hold timeare estimated assuming that the period, i.e. the effectiveoperation frequency, of the global clocks is 800 MHz. If thefrequency is relaxed, the setup time and the hold time are alsorelaxed correspondingly, and therefore, the foregoing phaseadjustment may be performed with the maximum frequency expectedupon designing the memory module.

[0336] In the foregoing examples, the description has been givenonly about the memory systems in which the buffer is provided onthe memory module. In other words, the description has been givenonly about the memory systems that can increase the number ofmemory modules. However, the present invention is also applicableto a memory system having a configuration in which a single memorymodule mounted thereon with no buffer is controlled by a memorycontroller. In the memory system of this type, the functions of thebuffers in the foregoing examples may be implemented by the memorycontroller.

[0337] Referring to FIG. 64, there is shown one example of theforegoing memory system as still another example of the presentinvention. The shown memory system 1000 comprises a memorycontroller 1011, a clock generator 102, and a single module 1031 onwhich four DRAMs 110 (1 to 4) and five DRAMs 110 (1' to 5') aremounted on the left side and the right side, respectively. In otherwords, the shown memory system 1000 is substantially the same aseach of the memory systems shown in other figures wherein thememory controller 1011 is provided instead of the buffer 105. Inthe shown example, the memory controller 1011 and the DRAMs 110 arerespectively connected to each other via data wirings DQ having thesame length, and arrival times of data signals DQ from the memorycontroller 1011 at the respective DRAMs 110 are substantially thesame.

[0338] On the module 1031, the left-side four DRAMs 110 (1 to 4)are connected to the memory controller 1011 via common clock wiringand common command/address wiring, while the right-side five DRAMs110 (1' to 5') are also connected to the memory controller 1011 viaother common clock wiring and common command/address wiring. Thatis, it is seen that the left-side DRAMs 110 (1 to 4) and theright-side DRAMs 110 (1' to 5') are connected to the memorycontroller 1011 via the separate clock wirings and command/addresswirings.

[0339] With respect to the DRAMs 110 (4) and (5') disposed at farends in the memory system having the shown topologies, there arelarge differences in wiring length between the clock wiring and theaddress/command wiring relative to the memory controller 1011, andthe data wiring DQ relative to the memory controller 1011.

[0340] Therefore, a propagation delay difference between the clocksignal (command/address signal) and the data signal DQ from thememory controller 1011 at the DRAMs 110 (4) and (5') becomes largerthan that in the foregoing modules.

[0341] For example, in the shown example, assuming that a DRAMpitch is 13 mm and a signal unit propagation time tPD is 14 ps/mm,a delay of the command/address signal on the module 1031 becomes728 ps (13.times.4.times.14) at the DRAM 110 (4), while it becomes910 ps (13.times.5.times.14) at the DRAM 110 (5'). Assuming thatpropagation delays of the clock and command/address signals and thedata signal DQ from the memory controller 1011 to input terminalsof the module 1031 are equal to each other, the foregoing delays onthe module 1031 become skew differences between the command/addresssignal and the data signal DQ, respectively.

[0342] The memory system 1000 according to the fourth example ofthe present invention processes those skew differences using thedomain crossing technique that employs the foregoing DPS (DataPhase Signal). Referring to FIG. 65, there is shown a writeoperation in the memory system 1000 shown in FIG. 64. First, theclock generator 102 generates reference clocks (i.e. system clocks)of 800 MHz and feeds them to the memory controller 1011. The memorycontroller 1011 divides the reference clocks (system clocks) tohalf in frequency to produce system clocks of 400 MHz, whileproduces a write command (WRT) synchronously with the producedsystem clocks.

[0343] Further, in the memory controller 1011 shown in FIG. 64, aDPS (WDPS) advanced by 90 degrees relative to the clock signal isproduced, and this WDPS is transmitted to the DRAMs 110. In FIG.65, there is shown a case wherein the WDPS is transmitted only tothe DRAMs 110 (1' to 5'). By producing the DPS having an advancedphase relative to the clock signal, there can be ensured margins toa setup time and a hold time for domain-crossing a command/addresssignal from the clock phase to the DPS phase, i.e. the data signalDQ phase in the DRAM 110. That is, by using the DPS with theshifted phase relative to the clock signal, it is possible toperform timing adjustment for the domain crossing.

[0344] In FIG. 65, when the write command (WRT) is received at theDRAM 110 (1') synchronously with the clock signal, the WRT iscaused to match with the DPS received at the DRAM 110 (1') so as tobe produced as a DRAM internal command signal (DRAM internalCommand). After a lapse of 6 write latency time subsequently to theproduction of the DRAM internal command signal, a data signal writeoperation is implemented in the DRAM 110 (1').

[0345] On the other hand, the clock signal and the WRT are given tothe DRAM 110 (5') with a delay as compared with the DRAM 110 (1'),and the DPS is also given thereto with a delay of 965 ps relativeto the clock signal. In this state, at the DRAM 110 (5'), the WRTis caused to match with the DPS so as to be produced as an internalcommand signal (DRAM internal Command). As clear from FIG. 65, itis understood that, by implementing the foregoing domain crossing,a sufficient setup time and hold time are ensured in the DRAMs 110(1') and (5').

[0346] Referring to FIG. 66, there is shown a read operation in thememory system 1000 shown in FIG. 64. Like in the write operation,the memory controller (MC) 1011 produces a read command (RED)synchronously with the clock signal of 400 MHz. Further, the memorycontroller (MC) 1101 produces a DPS (RDPS) having a phase advancedby 90degrees relative to the clock signal.

[0347] The clock signal (CLK) and the read command (RED) from thememory controller 1011 arrive at the DRAMs 110 (1' to 5') aftermutually different propagation delay times, while the DPS arrivesat the DRAMs 110 (1' to 5') at substantially the same timing viathe equal-length data wirings.

[0348] Taking the far-end DRAM 110 (5') as an example, the DRAM 110(5') receives the read command (RED) synchronously with the clocksignal, and further receives the DPS. Like the DPS given to theother DRAMs 110, the subject DPS is fed to the far-end DRAM 110(5') after a lapse of a delay time of 700 ps subsequently to theproduction thereof at the memory controller (MC). In the far-endDRAM 110 (5'), the RED received synchronously with the clock signalis caused to match with the DPS received at the far-end DRAM 110(5'), so as to be produced as an internal command signal (DRAMinternal Command). In this manner, the domain crossing is carriedout from the timing of the clock signal to the timing of theDPS.

[0349] On the other hand, in the memory system 1000 shown in FIG.64, arrival times of data signals DQ from the memory controller1011 at the respective DRAMs 110 are substantially the same.However, in the memory controller 1011, it is necessary to identifya data signal DQ received from each DRAM 110 as to which of theread commands (RED) the received data DQ corresponds to.Accordingly, the memory controller 1011 receives the DPS from eachDRAM 110 and causes the timing of the received DPS to match withthe timing of a WDPS of the memory controller (MC), i.e. performsthe domain crossing. At the memory controller (MC) 1011, a datasignal DQ read from the DRAM 110 is received synchronously with aDPS(R) from the DRAM 110, and caused to match with the timing ofthe DPS(W) of the memory controller (MC) 1011. That is, at thememory controller (MC) 1011, the data signal DQ received at thephase of the DPS(R) is shifted to the phase of the DPS(W), i.e.returned to the phase of the clock signal.

[0350] Therefore, in the memory controller (MC) 1011, by countingthe number of clocks from the issuance of the read command (RED),it is possible to identify the data signal DQ as to which of theread commands (RED) it corresponds to.

[0351] In FIG. 66, it is assumed that an interval between thememory controller (MC) 1011 and the module 1031 is 100 mm. In thiscase, a delay time from transmission of a DPS(W) to reception of aDPS(R) having a corresponding phase at the memory controller (MC)1011 is 1400 ps, and a setup time and a hold time for domaincrossing in this case become 1400 ps and 1100 ps, respectively, sothat a sufficient timing margin can be obtained.

[0352] In FIG. 66, the DPS(W) is transmitted to the DRAMs 110 fromthe memory controller (MC) 1011, and the DPS(R) having the samephase as the received DPS(W) is transmitted from the DRAMs 110 tothe memory controller (MC) 1011.

[0353] Therefore, it is understood that this embodiment employs thesystem wherein the DPS is transmitted bidirectionally on the sameDPS wiring. Thus, actually, the configuration is employed whereinthe memory controller (MC) 1011 and each DRAM 110 transmit the DPSalternately, and the internal clock signal is reproduced based onthe received DPS.

[0354] Further, in the example shown in FIG. 64, two pairs ofcommand/address signals and clock signals are produced from thememory controller (MC) 1011 relative to the memory module 1031. Onthe other hand, like operations can be achieved when a pair ofcommand/address signal and clock signal are produced from thememory controller (MC) 1011.

[0355] Referring to FIG. 67, a memory system 1000 according to afifth example of the present invention is provided with aconfiguration in which nine DRAMs 110 (1) to (9) are mounted on amodule 1031 like in FIG. 64, wherein a command/address signal and aclock signal that are common to all the DRAMs 110 are fed from amemory controller 1011 to those nine DRAMs 110 via a left end ofthe module 1031. That is, the nine DRAMs 110 share thecommand/address signal and the clock signal. In this case, assumingthat the propagation delay occurs like in FIG. 64, a propagationdelay difference of (728+910) ps (=1638 ps) occurs in thecommand/address signal and the clock signal relative to a datasignal DQ at the farthest end DRAM 110 (9). Even if the domaincrossing is implemented with the period of 2500 ps of the clocksignal subjected to the frequency division to half, it is difficultto ensure a timing margin for domain crossing that is sufficientfor dealing with such a large propagation delay difference. Forensuring a timing margin for sufficient domain crossing, it isconsidered to use clocks having a period that is longer than thatobtained by the frequency division to half.

[0356] On the other hand, as another technique to ensure asufficient time margin necessary for domain crossing while usingthe clocks subjected to the frequency division to half, it isconsidered to divide the DRAMs 110 on the module 1031 into twogroups (herein called "first and second DQ channels") as shown inFIG. 67. In this case, in the memory controller (MC) 1011, phasesof DPS(W) given to the first and second DQ channels are mutuallyshifted relative to the clock signal. That is, in the shown memorycontroller (MC) 1011, phase offset values of the DPS(W) relative tothe clock signal are set to values suitable for the first andsecond DQ channels.

[0357] In the shown example, the phase of the DPS(W) is advanced by90 degrees relative to the clock signal for the first DQ channel,while the DPS(W) is transmitted in phase with the clock signal forthe second DQ channel.

[0358] Referring to FIG. 68, description will be given about awrite operation in the DRAMs 110 (1) to (4) belonging to the firstDQ channel. First, the memory controller (MC) 1011 divides to halfin frequency a reference clock signal of 800 MHz generated by aclock generator 102, thereby to produce a clock signal of 400 MHz.This clock signal is fed to the DRAMs 110 (1) to (4) belonging tothe first DQ channel via clock wiring. The memory controller (MC)1011 further feeds a write command WRT onto command/address wiringsynchronously with the produced clock signal.

[0359] On the other hand, DPS(W) are fed to the DRAMs 110 (1) to(4) of the first DQ channel via DPS wirings each having a length ofabout 100 mm. In this case, as clear from FIG. 68, the phase of theDPS(W) is advanced by 90 degrees (i.e. 625 ps) relative to thephase of the clock signal.

[0360] The DPS(W) produced at the memory controller (MC) 1011arrive at the DRAMs 110 (1) to (4) of the first DQ channel via theDPS wirings. On the other hand, the clock signal and the writecommand (WRT) arrive at the DRAMs 110 (1) to (4) of the first DQchannel via the clock wiring and the command/address wiring.Inasmuch as the clock wiring and the command/address wiring areeach longer than the DPS wiring, a propagation delay time of theclock signal and the write command (WRT) becomes long, so that apropagation delay time difference between the DPS and the writecommand (WRT) is increased to 807 ps at the DRAM 110 (1). At theDRAM 110 (1), a DRAM internal command is produced at a time instantwhere 1693 ps has elapsed after reception of the WRT. This meansthat, at the DRAM 110 (1), the write command (WRT) matched with theclock signal is caused to match with the timing of the receivedDPS.

[0361] Further, among the DRAMs 110 belonging to the first DQchannel, a propagation delay time difference between the DPS(W) andthe clock signal at the far-end DRAM 110 (4) becomes 1353 ps. Alsoin this case, by matching the write command (WRT) with the timingof the DPS, a time margin of 1147 ps can be ensured. With this timemargin, it is possible to ensure a setup time and a hold timenecessary for domain crossing.

[0362] Referring to FIG. 69, there is shown a read operation in theDRAMs 110 (1) to (4) belonging to the first DQ channel. Also inthis example, a read command (RED) is fed to the DRAMs 110 (1) to(4) from the memory controller (MC) 1011 synchronously with theclock signal, and a DPS is produced as being advanced by 90 degreesrelative to the clock signal, which is like the case of the writeoperation. Here, assuming that a distance between the memorycontroller (MC) 1011 and the module 1031 is 100 mm, and a signalunit propagation time tPD is 7 ps/mm, the DPS arrives at the DRAM110 (4) after 700 ps. The DRAM 110 (4) causes the read command(RED) to match with the DPS to thereby produce an internal readcommand, and transmits a DPS(R) to the memory controller (MC) 1011.This DPS(R) is received at the memory controller (MC) 1011 after alapse of 1400 ps subsequently to the production of the DPS(W). Adata signal DQ from the DRAM 110 (4) is received at the memorycontroller (MC) 1011 at timing matched with the DPS(R).

[0363] By domain-crossing the timing of the received DPS(R) to thetiming of the DPS(W), the memory controller (MC) 1011 causes thetiming of the data signal DQ to match with the timing of theDPS(W). By this, a time margin of (1400+1100), i.e. 2500 ps, can beobtained also during the read operation.

[0364] Now, referring to FIG. 70, description will be given about awrite operation of the DRAMs 110 (5) to (9) belonging to the secondDQ channel in the memory system 1000 shown in FIG. 67. As clearfrom FIG. 70, with respect to the second channel, the memorycontroller (MC) 1011 produces a clock signal of 400 Hz and a writecommand WRT matched with the clock signal, and further produces aDPS(W) having the same phase as the clock signal. In this manner,in this example, an offset value corresponding to 90degrees of theclock signal is set between the DPS(W) for the DRAMs 110 (5) to (9)belonging to the second DQ channel and the DPS(W) for the DRAMs 110(1) to (4) belonging to the first DQ channel, thereby to enabledomain crossing even if there is a large propagation delaydifference between the clock signal and the data signal DQ.

[0365] Specifically, the clock signal (CLK) and the WRT from thememory controller (MC) 1011 arrive at the DRAMs 110 (5) to (9) ofthe second DQ channel via the long wirings, while the DPS(W) aregiven to the DRAMs 110 (5) to (9) via the relatively short DPSwirings. In FIG. 70, operations of only the DRAMs 110 (5) and (9)are shown.

[0366] As clear from FIG. 67, the DPS(W) reaches the DRAM 110 (5)910 ps earlier than the clock signal and the WRT and, after 1590ps, is caused to match with the DPS(W) received at the DRAM 110(5). Therefore, at the DRAM 110 (5), it is possible to ensure asetup time and a hold time necessary for domain crossing.

[0367] On the other hand, as clear from FIG. 67, the clock signaland the WRT, after having been produced at the memory controller(MC) 1011, arrive at the DRAM 110 (9) with a delay of 1638 psrelative to the DPS(W). At the farthest-end DRAM 110 (9), thereceived WRT is caused to match with the received DPS(W), therebyto produce an internal command. In this event, since there is atime margin of 862 ps between the WRT and DPS(W), it is seen that asetup time and a hold time necessary for domain crossing areensured.

[0368] Referring to FIG. 71, description will be given about a readoperation in the DRAMs 110 (5) to (9) of the second DQ channel.Also in this case, a clock signal and a read command (RED) aretransmitted, in phase with DPS(W), to the DRAMs 110 (5) to (9) fromthe memory controller (MC) 1011.

[0369] Among the DRAMs 110 of the second DQ channel, the DPS(W)arrives at the farthest-end DRAM 110 (9) 1638 ps earlier than theRED like in case of the WRT. As a result, the RED is caused toshift from the timing of the clock signal to the timing of theDPS(W) received at the DRAM 110 (9).

[0370] On the other hand, when the DPS(W) is produced at the memorycontroller (MC) 1011, the DPS(W) reaches the DRAM 110 (9) after alapse of 700 ps, and the received DPS(W) is, as it is, transmittedto the memory controller (MC) 1011 from the DRAM 110 (9) as aDPS(R), so that a DPS(R) delayed by 1400 ps is produced at thememory controller (MC) 1011.

[0371] A data signal DQ from the DRAM 110 (9) is transmitted to thememory controller (MC) 1011 at timing of the DPS(R). At the memorycontroller (MC) 1011, as shown in FIG. 71, the data signal DQtransmitted at the timing of the DPS(R) is caused to match with thetiming of the DPS(W) in the memory controller (MC) 1011. A timemargin at this time is, as shown in the figure, 2500 ps, andtherefore, it is seen that a time margin sufficient for performingdomain crossing can be ensured.

[0372] As described above, although a time difference correspondingto the offset is generated between the channels with respect to theread data signals DQ in the memory controller (MC) 1011, a timemargin necessary for domain crossing from the DPS(R) to the clockphase is sufficiently ensured.

[0373] As described above, since the memory controller 1011operates in response to the system clocks from the clock generator102 so as to achieve the operations like the buffer in the first tothird examples, the global clocks and the system clocks given tothe buffer and the memory controller 1011 can be collectivelycalled main clocks.

[0374] In the present invention, a memory system includes a memorycontroller and a module mounted with memory circuits and a buffer.Wiring including data wiring between the memory controller and thememory circuits on the module is achieved via the buffer, andwiring including data wiring connects buffers on modules in casemode. Accordingly, it is not necessary to branch the wiring permodule, and therefore, reflections caused by impedance mismatchingcan be prevented to enable a system that can operate at high speedat high frequencies. Further, according to the present invention, atransmission speed between the memory controller and the buffer isset to be higher than a transmission speed between the buffer andthe memory circuits. This makes it possible to increase the numberof modules to be connected to the memory controller. Further, it ispossible to configure a system that does not rely on a write/readspeed of the memory circuits.

[0375] According to one embodiment of the present invention, notonly the data wiring, but also the clock wiring and thecommand/address wiring connect buffers on the modules from thememory controller. This can make substantially equal distancesbetween the memory controller and the respective memory circuitsmounted on the module. Therefore, timing differences caused by adifferent delay time per wiring can be avoided. Further, accordingto another embodiment of the present invention, by providing aplurality of buffers on each module and connecting each buffer tomemory circuits on the module, a load applied to each buffer andthe wiring can be dispersed. Further, according to anotherembodiment of the present invention, memory circuits to be selectedsimultaneously are disposed over a plurality of modules, and abuffer of each module is individually connected to a memorycontroller. This makes it possible to disperse a load applied toeach buffer, without increasing the number of buffers.

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